SU1730726A1 - Pulse-position code decoder - Google Patents

Abstract

The invention relates to computing technology, in particular to devices for decoding pulse code sequences, and can be used in information processing devices. The invention allows both single-channel and multi-channel decryption of the input information, thereby expanding the use of the decoder. The decoder time of the pulse codes contains the shaper 1 pulses, delay element 2, K-bit registers 3 and 4 shift, block 5 of the elements OR, blocks 6 and 10 of the pulse shaper, inverter 7, buffer register 8, group 9.1 - 9.M multiplexers, group 11 1-11 M elements 12.1-12 X And in each 1 Il.

Description

VI with

About VI

GO

about

The invention relates to computing, in particular to devices for decoding pulse sequences, and can be used in information processing devices.

The aim of the invention is to expand the use of the decoder.

The drawing shows the functional diagram of the decoder.

Descrambler contains shaper

1 impulses, delay element 2, first and second K-bit registers 3 and 4 shift, block 5 elements OR, first block 6 of pulse shapers, inverter 7, buffer register 8, group 9.1-9. M multiplexers, second shaper 10 pulses, group 11.1 - 11.M elements 12.1 - 12.X And in each,

In the drawing, reference numeral 13 denotes the outputs of the decoder, positions 14-18 denote the clock input, the first information input, the second information inputs, the data inputs and the decoder recording input, respectively.

The decoder works as follows.

At the clock input 14 of the decoder received pulses of type square wave. At the output of the inverter 7, a meander is formed, shifted relative to the input one at a time

t g / 2;

where f is the period of the following clock pulses.

Next, the meanders arrive at the clock inputs of the first and second K-bit registers 3 and 4 of the shift. At the same time, the combined information inputs of these registers 3 and 4 through shaper 1, which normalizes the input pulses by duration, and element

The 2 delays receive the signal to be decoded and are recorded in the corresponding registers 3 and 4, and later, under the influence of the clock pulses, it shifts and appears at the outputs of the registers 3 and

4 through time T, defined by the formula T Kt

where K is the number of the corresponding register bit.

From the outputs of registers 3 and 4, the signals are sent to the corresponding inputs of the OR elements of block 5 of the OR elements, where they are combined. From the outputs of the block 5 elements OR to the outputs 13 of the decoder, signals from those elements 12.1 - 12 pass through the first block 6 of the drivers, the choice

which is carried out with the help of group 9.1-9. M multiplexers, register code 8. The first and second blocks 6 and 10 of the drivers and the driver 1 form signals of a certain duration under the action of signals arriving at their inputs. Shaper 1 generates pulses with a duration of Gf1 t / 2 which ensure their recording at least in one of registers 3 and 4. The second block of 10 drivers of input signals generates short pulses. The first block of 6 drivers generates pulses whose duration is determined by the AT error of the digital delay line (the first and second shift registers 3 and 4, block 5 of the elements OR) and can be determined by the following formula:

Gf2 2 AT

Using the delay element 2, the input signal delay is adjusted within half the duration of the clock pulse following period.

At outputs 13 of the decoder, signals are formed from the matched in time on the first and second inputs of the corresponding elements 18.1 to 19.X AND, i.e. delayed for a certain time and current signals, which corresponds to certain code intervals, while the output of the first element 12.1 And this group contains matched delayed signals arriving at input 16 and current signals arriving at input 15; at the output of the second element 12.2 And this group - delayed signals arriving at the input 15, and the current signals arriving at the input 16, etc. One of the channels of each code interval (elements 12.1 - 12.X of group 11.1 - 11.M of elements I) is selected using group 9.1 - 9.M multiplexers whose address inputs are connected to a register.

Thus, the resolution of the decoder At, defined as the minimum allowable distance between two successive pulses of a certain duration at the input of the decoder, at which their difference is possible at the output, is determined by the formula

At (p-1) T + TU

where ti is the duration of the input pulse.

Claims (1)

Invention Formula The decoder time pulse codes containing a pulse shaper, the output of which through the delay element is connected to the information inputs of the first and second K-bit shift registers, a block of OR elements, the outputs of which are connected to the corresponding inputs of the first block of shaper drivers, the outputs of the first K-bit register the shift is connected to the corresponding first inputs of the block of the OR elements, the outputs of the second K-bit shift register are connected to the corresponding second inputs of the block of the elements OR, clock the input of the first K-bit shift register is combined with the input of the inverter and is the decoder clock input, the output of the inverter is connected to the clock input of the second K-bit shift register, the input of the pulse shaper is the first information input of the decoder, characterized in that expanding the use of the decoder by providing multi-channel decryption, a buffer register, a group of multiplexers, the second block five 0 pulses and M groups (M 1, K) of elements I and X elements I (X - i, N) in each, the outputs of the first block of pulse formers are connected to the first inputs of the elements And of the corresponding groups of the block, the outputs of the second block of formers of pulses are connected to the second the inputs of the corresponding elements AND of each group, the outputs of the elements AND groups are connected to the same information inputs of the corresponding multiplexers of the group, the groups of outputs of the buffer register are connected to the same address inputs of the corresponding multiplexers the groups, the inputs of the second block of drivers are the second information inputs of the decoder, the information inputs of the buffer register are inputs of the data of the decoder, the clock input of the buffer register is the write input of the decoder, the outputs of the multiplexers of the group are outputs of the decoder.