SU900408A1 - Digital delay line - Google Patents

Description

(54) DIGITAL DELAY LINE

one

The invention relates to radio engineering and can be used for. controlled output of pulse signals, in particular digital filters and other devices where a time delay of pulses is required that is longer than the period of the pulse signal.

The known digital delay line of random pulse signals containing a clock generator, time-code converters and code-time, shift registers connected between the converters and the control channel of the number of delay-ticks 1.

The main disadvantage of this delay line is the limited bandwidth, which significantly limits their scope.

Closest to the invention in technical essence and the achieved result is a digital delay line of random pulse signals containing a clock generator, time-code converters and time code, m shift registers (additional) connected by inputs to the time-code converter, and outputs the transducer code is the time CONTROL (main) shift register connected to the line input

delays through the driver, and the elements connected to the output of the control register and the output of the converter code - time 2.

The disadvantage of the known delay line is the limitation of its bandwidth, which, when delaying random and frequency-modulated pulse signals, reduces

10 its scope. Expansion of the bandwidth by increasing the clock frequency leads to a significant increase in the equipment of the shift recorders, a characteristic feature of random and frequency modulated pulse signals is the irregularity of their period with a significant difference between their largest and smallest values.

20

To achieve 1LO% throughput of the delay line of random or frequency-modulated pulse signals, the period of ticks should not exceed the smallest interval of time between pulses, which will require a significant increase in the number of register bits compared to a periodic signal with an average period. These are well-known ways to build digital

delay lines for periodic pulsed signals, which were previously considered, are unacceptable for emitting random pulsed signals due to a significant increase in the volume of register equipment.

The purpose of the invention is to expand the bandwidth of the delay line when processing random and frequency-modulated pulse signals.

This goal is achieved by the fact that in a known delay line containing a clock generator, time-to-code converters, code-time, m shift registers, control register and AND element, the input pulse generator is connected to the clock generator and inputs, time-converter converters, code and code time, and through the first OR element with the clock inputs of the first group m of the shift registers and the control register and directly with the clock inputs of the remaining bits of the indicated registers, the first OR element being formed eh second input coupled to the input of the delay line, and the second OR element - to the outputs of AND gates connected to outputs of the code converter - time and output delay lines.

Figure 1 presents the block diagram of the device; in fig. 2 - time schedules of the passage of signals.

The delay line contains 1 clock generator, performed on the controlled frequency divider, time converter 2 - code, converter 3 time code, counters 4 and blocks 5-7 of converter code comparison 5 time code, elements AND 8, 9, 10, control register ll -l-Hl-n shift registers 12-lr 2-m, 13-1t13-t shift, shaper 14 packs of pulses, shaper 15, elements of the IPI 16, 17, input 18 and output 19 of the delay line.

Shift register bits are grouped into groups. The first group-e includes bits of registers 11-1, 11-2, 11-3, 12-1, 12-2, 12-3, 13-1, 13-2, 13-3. The last output group includes bits 11-2, ll- (nl), 11-n, 12- (t-2), 12- (t-3), 13- (t-2), 13- (t -1), 13t. The code comparison blocks are connected by the second inputs with the corresponding bits of blocks 5-7 of registers, the shift of the last group. Elements 8-10 are connected by the first inputs to the corresponding outputs of blocks 5, 6, 7 of the code comparison, and the second to the corresponding outputs of the last group of the control register 11-1t11-p,

The time graph (Fig. 2) shows the reference frequency pulses (c. 20), clock frequency pulses (c. 21), the pulses at the output of the imager 14 bursts of pulses (c. 22), the impulses at the output of the imager 15 input signals (gr. 23) the pulses at the output of the code scan element 17 (groups 24) at the outputs of the counters of the converters 2 and 3 are provided by the graphs 25 and 26, the pulses iha of the outputs of elements 8-10 are represented by the graphs 27, 28, 29 and the pulses at the output 19 of the delay line (gr 30) after the delay time t.jciA.

Line delay works as follows.

With the device turned on, the counters of the converters 2 and 3 with the clock pulses of the generator 1 are set to the initial zero state. At the same time, at the output of the imaging unit 14, bursts of pulses are formed (groups 22), which flow through the element 17 to the clock inputs of the bits of the first group of registers and clear them, since logical O are set up at their recording inputs. Clearing the registers of the first group is completed during the zero state no counter. With the arrival of pulses on the counting inputs of the counters of the converters 2 and 3, synchronous scanning of the code begins. At this point, the first group of register bits is ready to receive input delay line pulses during the next clock period. The input signal pulse arrives through the output of the imaging unit 15: to the input of the control register record, and the pulse delayed by half the period of the reference frequency from its second output enters the input of the element 17 and further to the clock inputs of the registers of the first group. By this impulse, the code from counter 2, recorded in the m registers, and the logical unit recorded in register 11 are advanced one step. With the arrival of the second input pulse, the write and shift operation is repeated.

The rewriting of the recorded code from the first group of registers to the second is performed by the next burst of pulses from the shaper 14 through element 17. And again the first group of shift registers is prepared to receive the next input pulses.

brain teaser

recorded with

the arrival of input pulses in the register 11-1-t11-p and the sweep code of the counter Converter 2, corresponding to the arrival time of the input pulses in m registers 12-13, arrive through the delay time into the last group of registers. Logic i output from register 11 is the enable signal for elements 8-10.

The bit outputs of the code of the last group T of registers are fed to the second inputs of blocks 5 - 7.

Claims (2)

With the arrival of the sweep code from the transducer counter 3 to the nepi inputs of blocks 5-7, pulses are generated at their outputs with equal codes that pass through the open elements 8-10 and 16 to you delay line 19. The control register 11 thus makes it possible to distinguish the zero code on the registers in the presence and absence of an input pulse. The delay time of the line is proportional to the period of clock cycles T and the number of groups of bits of shift registers BUT since A. where n is the number of bits of registers K - the number of bits in their group, l. The value of K is selected in the range of 2 or more. The delay time of the line can be adjusted both by the number of register bits and the period of ticks on the controlled frequency divider. Thus, the use of group recording of sweep codes corresponding to an arbitrary location of pulses in the clock period makes the proposed delay line more adapted to the delay of random pulse signals in comparison with the known one. A digital delay line comprising a clock generator, a time-code converter, a code-time converter, m shift registers, a control register, and AND elements, characterized in that, in order to expand the throughput of a random or frequency-modulated pulse signal, shunt imnyhbcoB shaper, first and second elements OR, P: Rich, shuffle shaper is connected to clock generator and inputs reset of time transducers - code and code - time, and output through the first AND element LI to clock inputs of the first group of m shift registers and the control register and directly to the clock inputs of the remaining bits of the indicated registers; with the 3rd, the first element OR is connected via its driver with its second input to the input of the delay line, and the second element OR to the outputs of the AND elements, connected to the outputs of the converter code - time, and the output of the delay line. Sources of information, rinty in attention during the ex- pert 1. The author's certificate of the USSR 663076, cl. H 03 H 7/30, 1976. 2. Authors certificate of the USSR 568152, cl. H 03 H 7/30, 1976. 1- -J1L X -t -Ul-j F Jil X Ji in j JLJIJLUL L 25 Z6 П Z8 Z9 30 5M J t