SU1504798A1 - Pulse shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in a communication technique. The purpose of the invention, the extension of functionality, is achieved by restoring the input signal at a given phase shift and controlling the duration of the output pulse. The pulse generator contains a counting pulse generator 1, controlled in frequency, a single pulse generator 2, a shift register 3, a buffer register 4, and a switch of 5 channels. The proposed pulse shaper can be used to simulate the transmission of signals over communication channels. In this case, the phase shift and reduction of the signal duration will be equivalent, respectively, to the delay and attenuation of the signal in the communication channel. The former is easily implemented on typical shift chip registers and channel switches. The controlled oscillator can be implemented on the basis of a code converter ("0", "1") into the frequency. 2 Il.

Description

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The invention relates to a pulse technique and can be used in a communication technique.

The purpose of the invention is to expand the functionality of the imager by restoring the input signal at a given phase shift and controlling the duration of the output pulse.

FIG. 1 shows a diagram of the imager; in fig. 2 is a diagram explaining his work.

The pulse shaper contains a counting pulse generator 1, controlled by frequency, a single pulse shaper 2, a shift register 3, a buffer register 4, and a switch of 5 channels.

The output of the generator 1 is connected to the input of the imaging unit 2 and the contact input of the shift register 3, the output of the imaging unit 2 is connected to the rewrite input A of the buffer register 4. The outputs of the shift register bits 3 are connected to the corresponding inputs of the switch 5, the outputs of the buffer register 4 to the control inputs switch 5, the output of which is connected to the control input of the generator 1. The input signal is fed to the second input of the imaging unit 2 and the serial input of the shift register 3, to the inputs of the parallel recording of the buffer register 4 - the N code, limit - yuschy shift pulse output relative to the input.

The pulse shaper operates as follows.

The input signal (pulse or video signal) is connected to the driver 2 and the serial input of the shift register; 3. At the output of the imager, a single pulse is generated synchronized with the pulses of the generator 1, which is fed to the overwriting input A of the buffer register 4, writing the code N (, - g into it. At the same time, the lower bit of the shift register is filled with the pulse from the generator 1. Pa 3

When writing the N code to the buffer register 4, one of the shift register outputs is connected to the output of the driver via switch 5, and the number of the pulses of the generator 1 defined by

N,

Sa &

the output of the device is transmitted

an input signal that simultaneously enters the generator control input and changes the counting pulse frequency by a factor of m.

There are two possible occurrences of the output pulse:

1) at the time when the input pulse is not finished (Fig. 2, a)

2) after the end of the input pulse (Fig. 2.6).

In the first case, the input pulse is recorded and shifted in the shift register 3 by counting pulses of the frequency changed by m times, and the duration of the output pulse is equal to

acc.

GT

ex. (one

for a given shift T (, g, defined by the code.

In the second case, the input pulse completely recorded in the shift register 3 is output from it by counting pulses of the frequency changed by m times, and the duration of the output pulse is equal to

Tgnx. 2 Tg, 2 / ta

for a given shift T (, dv, defined by the code Nj, jg.

After the termination of the pulse, the frequency of the counting impulses of generator 1 restores its initial value.

Thus, the shaper has advanced functionality compared with the prototype and is able to perform the following functions:

the formation of the output pulse with a given (controlled) delay on the Nj.g cycles relative to the input signal and a duration equal to the duration of the input signal (approx. 1)

the formation of the output pulse with a given (controlled) delay per clock relative to the input signal and a controlled duration equal to T

T „.- T, d. (1- -), with

6x BX - Asy of input pulse duration is greater than the delay time;

the formation of the output pulse with a given (controlled) delay on Ng jtacts relative to the input signal and controlled duration, Tg, x Tj, / m, with duration

five

input pulse is less than the delay time.

The former is designed to simulate the transmission of signals over communication channels, while the phase shift and reduction of the signal duration are equivalent to the delay and attenuation of the signal in the communication channel, respectively.

The former is easily implemented on shift chip registers and channel switches, for example, 155 series.

The control generator can be implemented on the basis of a code converter (O, D), into a frequency.

Claims (1)

Invention Formula A pulse shaper containing a counting pulse generator connected to the input of a single pulse shaper, the second input of which is connected to the input bus, and and entrance Generator Output 047986 the clock input of the shift register, the buffer register, the rewriting input of which is connected to the output of the single pulse shaper, and the inputs of the parallel writing to the shift code bus, as well as the output bus, characterized in that, in order to expand the functional 1Q capabilities by restoring the input signal at a given phase shift and controlling the duration of the output pulse, a channel switch is inserted into it, and  5 channel switches are connected to the outputs of the shift register, and the outputs of the buffer register are connected to the control inputs of the channel switch, the output of which is connected to the control input of the generator, controlled by frequency, on the output terminal, and the serial input of the shift register connector . with input bus. FIG. 2