SU1081639A2 - Device for translating serial code to parallel code - Google Patents

Abstract

1. A DEVICE FOR TRANSFORMING A SEQUENTIAL CODE TO PARALLEL. By auth.St. No. 809160, distinguished by the fact that, in order to increase noise immunity, an additional output bus and an R5 trigger are introduced, the first input of which is connected to the output of the last digit of the shift register, the second input of the RS flip-flop is connected to the bus. additional output bus and to the second input of the mode trigger. 2. The device according to claim 1, that is, with the fact that (P + 2) -th raster is entered into the shift register, the input of which is connected to the output (n + Ogo discharge, and the output is connected with the release of the last digit of the shift register. 9, (L with fl e X) s::; o bv

Description

The invention relates to automation and computing, and can be used in digital channel transmission systems for converting a code sequence to a parallel one. According to the main auth. No. 809160, a device is known that contains a shift register, a mode trigger, an And element, a clock pulse generator, a code pulse bus, a bus. A message starts, the And output of the I pulse is connected to the information input of the shift register and to the input of the pulse generator, the output of which is the keys to the clock input of the shift register, the first input of the mode trigger is connected to the write input of the shift register and to the bus. The message starts, and the output is connected to the second input of the AND element, whose first input is connected to the code pulse bus lj. A disadvantage of the known device is low noise immunity due to the fact that using shift 1 in (n + 1) -th bit to form a signal. The end of the code combination does not allow detecting possible failures in the shift register in the process of receiving a serial code B resulting in A false signal may be generated. End of code pattern. False (premature signal occurrence) The end of the code limit prevents the reception of a code in the shift register, blocks the clock generator despite the fact that not all the P-bits of the sequential code are written into the register. The purpose of the invention is to improve noise immunity. The goal is achieved by that in a device for converting a serial code into a parallel one, containing a shift register, a mode trigger, an AND element, a clock pulse generator, a code pulse bus, a bus, the message starts, the output of the AND element is connected to the information input of the shift register and to the input of the pulse generator, the output of which is connected to the clock input of the shift register, the first input of the mode trigger is connected to the write input of the shift register and to the bus the message started, and the output to the second input of the And element whose first input is connected to the code pulse bus, an additional output bus and an RS trigger are entered, the first input of which is connected to the output of the last bit of the shift register, the second input of the R5 trigger is connected to the bus Start of the message, and the output to the additional output bus and to the second input of the mode trigger. The (p- | -2) -th bit is entered into the shift register, the input of which is connected to the output of the (c + 1) -th digit, and the output is connected to the output of the last digit of the shift register. The drawing shows a functional diagram of the device. The device contains a shift register 1, mode 2 trigger, element 3, 4 clock pulse generator, code pulse bus 5, bus 6 message start, R5-trigger 7, additional output bus 8, the output of the And 3 element is connected to the information input of register 1 shift and to the input of the generator 4 clock pulses, the output of which is connected to the clock input of the register 1 shift. The output of the R5 flip-flop 7 is connected to the second input of the flip-flop 2 of the mode, the first input of which is connected to the bus 6 The beginning of the message. The device works as follows. On bus 6, the beginning of the message enters a signal that writes 1 to the first bit of the shift register 1, and to the remaining bits, O, and simultaneously sets the RS-trigger 7 and the trigger 2 modes to the initial states. As the code pulses arrive on the code pulse bus 5, the shift register 1 receives the incoming information. In the case of receiving the expected and-bits of a sequential code without a fault in (li + 1) -M and () th bits of the shift register 1, the code 10 will appear. The appearance of this combination indicates that the serial code has been completed in the allele code and is followed by Signal End of the code combination. With (n + 1) -th bit of the register. If in the process svdiga 1, predirektno recorded in register 1

3 10816394

shear, in the latter fails, the state and generates a signal Scrap,

then a combination of 10 in (n + D-M driven over bus 8 and setting (AND + 2) th register bits the emerging trigger 2 modes to the state

with prematurely and forms the bed - at which the element 3 is closed,

signal signal End code combination-5 prohibit reception of information, information. In this case, the generator 4 clock

pulses proc / itaeT generate Introduce extra output

clock pulses, which are real-bus and RS-trigger, interferes with the shift of information in register 1

shift, and 1 appears in (y1 + 2) -mu allows you to detect errors when

The de register register 1, the KB-trigger 7, for the transformation of a sequential one, is co-set to the opposite to a parallel one.

Claims (2)

1. DEVICE FOR CONVERSION OF THE SERIAL CODE TO PARALLEL by ed. No. 809160, characterized in that, in order to increase noise immunity, an additional output bus and RS-trigger are introduced, the first input of which is connected to the output of the last bit of the shift register, the second input of the RS-trigger is connected to the bus Start of message] and the output to the additional output bus and to the second input of the mode trigger. 2. The device according to claim 1, which is related to the fact that the (П + 2) -th bit is inserted into the shift register, the input of which is connected to the output of the (п + 1) th discharge, and the output connected to the output of the last bit of the shift register. '' 1 1081639