SU1290556A1 - Device for transmission and reception of discrete signals - Google Patents

Abstract

The invention relates to engineering. connection. The purpose of the invention is to increase throughput. The device contains on the transmitting side a detector of significant modulation moments, a control unit, a memory unit, a pulse sequence sensor, a code symbol input unit and a code symbol generation unit (BFXS), and a start symbol detector (DSS) and a code unit recording unit on the receiving side combinations (BZKK), an element EXCLUSIVE OR, a memory block, a block of output code characters, the converter number - interval and output matching block (ALL). The goal is achieved by performing the issuance of additional symbols introduced at the transmission and restoring the original zone number of the significant modulation moment. The device differs in p. 2 - 5 f-ly performing BFKS, DSS, BZKK and VSB, illustrations of their implementation, as well as the transmitting and receiving sides of the device. 4 hp f-ly, 6 ill. i (L N9 CO O O1 ate O)

Description

one

The invention relates to communication technology and can be used to transmit asynchronous discrete signals over a digital path.

 The purpose of the invention is to increase throughput.

FIG. Figure 1 shows the structural electrical circuit of the transmitting side of the device proposed .; in fig. 2 - the same, the receiving side of the proposed device; fig. 3 - the same, block forming code symbols; in fig. 4 - the same, the detector of the start symbol; fig.Z - the same, the output matching unit; in fig. 6 - the same as the block of writing code combinations.

The device for transmitting and receiving discrete signals contains on the transmitter side a detector of 1 significant modulation moments, a control unit 2, a memory block 3, a sensor 4 pulse sequences, a code symbol input block 5, a code symbol generation block 6, and detector 7 of the start symbol, block 8 of the writing of the code combination, element 9 EXCLUSIVE OR, block 10 of the memory, block 11 of the output of the code symbols, converter 12, the number is the interval, the output matching block 13.

The block of forming code symbols contains the element AND-NOT 14 and the register 15, the detector of the start symbol — the element NOT 16, the first and second elements AND 17 and 18, the D-flip-flop 19.

The output matching block contains the first and second elements NOT 20 and 21, the first, second, third and fourth elements AND-NOT 22, 23, 24, .25, trigger 26.

The block of writing the code combination contains the register 27 and the element NOT 28.

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25

The device works as follows.

In the initial state transmission, the signals at the control inputs of the code symbol input unit 5 are missing and the information inputs of the code pulse generation unit 6 receive pulse sequences from the sensor outputs 4 pulse sequences that are used to encode the zone number in which the significant moment of the module of The signal from the fourth output of the sensor 4 pulse sequences is also used as

national sync pulses. When the positive moment of modulation arrives at the input of the transmitting side, a pulse appears at the first and third outputs of the detector 1 of the significant modulation moments, which is generated using mutually inverse pulse sequences. The impulse from the third output of the detector 1 of the significant modulation moments arrives at the input of the control unit 2 and thereby switches it on.

The control unit 2 using channel sync pulses from the output of sensor 5 and four pulse sequences generates a control interval, which is a time interval equal to the period of the channel sync pulses following two full periods of the channel sync pulses after that location is a significant modulation moment. At the same time, a pulse from the third output of the detector 1 of significant modulation moments arrives at the input of memory block 3, in which the number of the zone of the positive significant modulation moment is fixed

30 using pulse sequences from the sensor outputs 4 pulse sequences. Pulse from the first output of the detector 1 significant modulation moments with some

jj; the delay generated by the pulse sequence from the fifth output of the sensor 4 of the pulse sequences is recorded in the code generation unit 6 of the code symbols from the input of the transmitting side and from the information outputs of the code symbol input 5. Since at this point in time, the code character block 5 skips

Since the signals from the sensor outputs 4 of the pulse sequences, then they are actually recorded in block 6 of the generation of code symbols. Next on channel clock pulses

50 information is being issued

from block 6 forming the code symbols of the B channel. When a negative significant modulation moment of a discrete signal arrives at the input of the transmitting side, a pulse is generated at the first and second outputs of the detector 1 of the significant modulation moments and in control unit 2 a negative is checked.

the significant modulation moment in the control interval and the formation of the next control interval begins. In the case of performing this check, a pulse appears at the output of control unit 2. At the same time, the pulse from the second output of the detector 1 of the significant modulation moments is recorded by fixing the number of the negative moment of the modulation in memory block 3 and outputting to its outputs signals corresponding to the zone number of the previous significant modulation moment. The zone number is represented in the lock by the zone number in the form of a two-digit binary number, ha.

Next, there is a redistribution of signals on the block 5 input code characters. If there is a zero signal at its first control input, its information inputs transmit signals from sensor A outputs of pulse sequences. If there is a single signal at the first control input of the unit 5 for inputting the code symbols, it works depending on the other two control signals as follows. If a two-bit binary number is fed to the control inputs of the code symbol input unit 5, a single signal is generated at the first additional output of the transmitting side and a signal from the first additional input of the transmitting side and the fourth sensor output 4 is output to the outputs of the code character input unit 5. pulse sequences. When the control inputs of the code symbol input unit 5 are given a binary number, single signals are generated at the two additional outputs of the transmitting side and the signals from the two additional inputs of the transmitting side are output to the outputs of the code character input unit 5. If the control inputs of the code character input block 5 receive a binary number or, the signals at the additional outputs of the transmitting side are not generated, and the outputs from the sensor 4 output of the pulse sequences are connected to the outputs of the code character input block 5. The pulse from the first output of the detector 1 significant modulation moments with some delay is recorded information from the outputs of the block 5 input code symbols in

block 6 of generation of code symbols At the end of the control interval, information about the zone number of the last significant modulation moment in the zone number lock is erased by signals from block 2 of the control. Further, on channel clock pulses, the information from block 6 of the generation of code symbols is read into the channel. t

When the starting code combination arrives at the input of the receiving side, after a series of symbols is exposed to channel clock pulses from the fourth output of the sensor 4 pulse sequences, it is recorded in the code combination recording unit 8. At the moment of recording the start symbol, the last bit of the block 8 of the recording of the code combination at the output of the detector 7 of the start symbol appears a pulse that puts the output matching block 13 into the operating state. Next, the decoding process begins. At this point in time, the fourth character of the block B contains a start character in the code combination, the second and third are the qualifying characters, and the first is either the start character of the next start code combination or a confirmation character. The signals from the second and third bits of the 8-record block of the code combination are fed to the inputs of the block 11 of the output of code symbols. The block 11 of the output of code symbols connects these signals without changes to the inputs of the converter. Number 12 is an interval, the other inputs of which receive pulse sequences from the sensor outputs 4 of pulse sequences. At the moment of simultaneous coincidence of signals from the outputs of block 11 of the code symbol with signals from the outputs of sensor 4 of pulse sequences, the output of converter 12 is a number — an interval forms a pulse that enters the output of the output matching unit 13. At the first output of the output matching unit 13 a significant moment is generated modulations of the discrete signal, as well as pulses are generated at the second and third outputs. From this point in time, the process of analyzing the received code combination begins. The signal from the second output of the output matching unit 13

- fO

memory unit 10 is reset when there is a zero signal combination at its outputs. The signal from the third output of the output matching unit 13, which is formed with some delay in relation to the signal from the second output, on element 9 EXCLUSIVE P1I compares the signals from the first and last outputs of the writing unit 8 to the code combination. If these signals do not coincide, the output of element 9 EXCLUSIVE OR forms a pulse that enters memory block 10, to the other inputs of which pulse sequences from the sensor outputs 4 of pulse sequences are supplied. Through these pulse sequences, the zone number is fixed in memory block 10. If there is no pulse from the output of element 9, the EXCLUSIVE OR combination of signals at the output of memory block 10 remains zero. The combination of signals at the outputs of memory unit 10 remains unchanged until the beginning of the analysis of the next start code combination. According to the signal from the third output of the output matching unit 13, the information is aligned on the last three bits of the block 8 of the writing of the code combination so that the specifying symbols are not perceived by the detector 7 of the start symbol as start symbols. Next, the following code pattern is recorded in the channel clock pulses in the code pattern recording unit 8.

At the moment of recording the start symbol, the last bit of the block 8 of the recording of the code combination at the output of the detector 7 of the start symbol appears a signal that sets the output matching block 13 to the working state. The signals from the second and third bits of block 8 of the code entry

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oxen binary number or. the signals are unchanged from the outputs of block 8 of the recording of the code combination to the inputs of the converter 12 number — the interval, as it was when receiving the previous code combination.

When the code inputs of the output 11 of the code symbols reach the first additional output of the receiving side, a single signal is generated, and the information outputs of the output block 11 of the code symbols turn on the signals from the third bit of the code combination recording 8 and from the first information input of the block 11 output code characters connected to a source of logical units. Upon receipt of the control code inputs of the output unit 11 of the code symbols, single signals are generated at both additional outputs of the receiving side, and the information outputs of the output unit 11 of the code symbols switch signals from the information inputs of the output unit 11 of the code symbols connected to the source of the logical unit.

30 When control signals are received at the additional outputs of the receiving side, the receiver of the additional channel receives symbols transmitted over the additional channel,

2 Thus, the issuance of additional symbols introduced at the transmission and the restoration of the original zone number of the significant modulation moment is carried out. Next, the device works like it does when receiving the first code combination.

Claims (2)

Formula invented and. 45 1 A device for transmitting and receiving discrete signals, containing on the transmitter side a detector of significant modulation moments, the first output of which is connected to a control 25 combinations, where at the moment the input of the code-forming unit are refining symbols, oxen, the information input of which is fed to the inputs of the output block 11 is connected to the information input of the grandfather symbols. The control inputs of the vector of significant modulation moments, block 11 of the output of code symbols receive signals from memory block 10, which characterize the zone number and on the receiving side, a start symbol detector, a code combination recording unit, a number converter — an interval, the output of which is connected to the first input of the output matching unit, distinguishes the weight from those. previous significant modulation moment. When entering the control inputs of the block 11 of the output code five 0 oxen binary number or. the signals are unchanged from the outputs of block 8 of the recording of the code combination to the inputs of the converter 12 number — the interval, as it was when receiving the previous code combination. When the code inputs of the output 11 of the code symbols reach the first additional output of the receiving side, a single signal is generated, and the information outputs of the output block 11 of the code symbols turn on the signals from the third bit of the code combination recording 8 and from the first information input of the block 11 output code characters connected to a source of logical units. Upon receipt of the control code inputs of the output unit 11 of the code symbols, single signals are generated at both additional outputs of the receiving side, and the information outputs of the output unit 11 of the code symbols switch signals from the information inputs of the output unit 11 of the code symbols connected to the source of the logical unit. 0 When control signals are received at the additional outputs of the receiving side, the receiver of the additional channel receives symbols transmitted via the additional channel,  Thus, the issuance of additional symbols introduced at the transmission and the restoration of the original zone number of the significant modulation moment is carried out. Next, the device works as it does when receiving the first code combination. Formula invented and. 5 1 A device for transmitting and receiving discrete signals, containing on the transmitter side a detector of significant modulation moments, the first output of which is connected to a control five 50 by the input of the code symbol generation unit whose information input is connected to the information input of the detector of significant modulation moments, and on the receiving side, a start symbol detector, a code combination recording unit, a number converter — an interval, the output of which is connected to the first input of the output matching unit, distinguishes the weight from those. that, in order to increase throughput, a control unit, a memory unit, a code symbol input unit and a pulse sequence sensor are entered on the transmitting side, the first and second outputs of which are connected respectively to the first and second inputs of the detector of significant modulation moments, the second and third the outputs of which are connected to sooot- corresponding to the first and second inputs of the control unit and to the corresponding first and second inputs of the memory unit, the third and fourth inputs of which are connected respectively to the first and second outputs of the control unit, the third output of which is connected to the first input of the code character input unit, the second and third inputs of which connected, respectively, to the first and second outputs of the memory unit, five of whose input is connected to the third output of the pulse sequence sensor and to the fourth input of the code character input unit, five to five the stroke of which is connected to the fourth output of the pulse sequence sensor, to the third input of the control unit and to the first input of the code characterization unit, the second and third inputs of which are connected respectively to the first and second outputs of the code character input unit, the fifth output of the pulse sequence sensor is connected to the fourth input of the code symbol generation unit, the output of which is the information output of the transmitting side, the information input of which is the information input The vector of significant modulation moments, the clock input of the pulse sequence sensor is the clock input of the transmitting side, the additional outputs and inputs of which are the additional outputs and inputs of the input-code characters block, and on the receiving side the EXCLUSIVE OR element is inserted, the memory block and the output block code symbols, the first and second outputs of which are connected respectively to the first and second inputs of the converter; the number interval, the third input of which is connected to the first input of the memory block, the second input of which The first is connected to the fourth input of the number-interval converter, to the first input of the code combination recording unit and to the first input of the detector of the start symbol, the first and second outputs of which are connected respectively to the second and third inputs of the output matching unit, the first output of which is connected to the second input block of the code combination recording and with the first input of the EXCLUSIVE OR element, the output of which is connected to the third input of the memory block, the first and second outputs of which are connected respectively to the first and second inputs code block input, the third and; quarter inputs of which are connected respectively to the first and second outputs of the code combination recording unit, the third output of which is connected to the second input of the detector of the start symbol and to the second input of the EXCLUSIVE OR element, the third input of which is connected to the fourth output of the block, the code record, the combination, the second output of the output matching block is connected to the fourth input of the memory block, with the fifth and sixth inputs of the code character input block being the inputs of the logical unit O, the third output of the output matching unit is the information output of the receiving side, the information input of which is the third input of the code pattern recording unit, the first and second outputs of which are the additional outputs of the receiving side, the control outputs of which are the control outputs of the code character input block and the first and second inputs of the memory unit are clock inputs of the receiving side, 2. The device according to claim 1, wherein the block of forming code symbols contains an AND-NOT element and a register, the parallel recording synchronized input of which is connected to the output of the IS-NOT element, the output of the last register bit is connected to the last input parallel recording of the register, the serial recording input of which is connected to the penultimate input of the parallel recording of the register, the recording mode setting input of which is connected to the first input of the NAND element and is the control input of the code symbol generation unit, the information th input of which is input to register sequential recording, the first, second and third inputs of which and a second input of AND-NO element are respectively first, second, third and fourth inputs of unit generating code symbols, the output of which is the final output of register. 3, the device according to claim 1, characterized in that the detector of the start symbol contains an element NOT, two elements AND and a D-flip-flop, the unit output of which is connected to the first input of the first element AND, the second input of which is connected to the output of the element NOT, whose input connected to the D-input of the D-flip-flop and the first input of the second element I, the second input of which is connected to the inverse output of the D-flip-flop5 The C input and the D-INPUT of which are respectively the nepBbiM and the second inputs of the start symbol detector are accordingly outputs of the first and second elements I. 4. The device according to claim 1, characterized in that the output matching block contains two NOT elements, four IS-NOT elements and an RS flip-flop, an R-input and an S-input of which are connected to the inputs of the first NAND element and to the outputs respectively the second and third elements NAND, the first inputs of which are connected to the first input of the fourth element NAND, the second input of which is connected to the input of the first element NOT and to you fO five 29055610 the second element, the input of which is connected to the output of the first element AND, while the first, second and third inputs of the output matching unit are respectively the first input of the fourth AND-NOT element, the second input of the second AND-NOT element and the second input of the third AND element NOT, the single output of the RS flip-flop is the third output of the output matching unit, the first and second outputs of which are respectively the output of the first element NOT and the output of the fourth AND-NOT element. 5. The device according to claim 1, characterized in that the block of writing the code combination contains a register and an element NOT, the output of which is connected to the synchronous input of the parallel recording of the register, the input of the recording mode of which is connected to the input of the element NO, the second, third and fourth D inputs of the register connected to the last register output and is the third output of the code pattern recording unit, informational, the input of which is the first V input of the register, the first. The C input and the second V input of which are respectively but the first and second inputs of the code pattern recording unit, the first, second and fourth outputs of which are the corresponding outputs of the register. 20 25 thirty fi & .4 cfjuff.S FIG. 6