SU1401633A1 - Discrete signal receiving device - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the reliability of reception. The device contains drive 1, number-to-interval converter (PSI) 4 and trigger 5. A code combination analyzer (ACC) 2 and sensor 3 of code sequences are entered. The reconstruction of the fronts of a discrete signal is performed by trigger 5, on the info. the input of which is supplied with a discrete input signal, and the sync input - a signal with information. I / O output 4. At the moment of signal edge recovery in I / O 4, a control signal is generated, which enters accumulator 1. By this signal, accumulator 1 records to the 1st, 2nd, and 4th register bits. The value of the start symbol A is recorded, i.e. Signal from the 3rd bit register This is necessary so that the qualifying symbols are not mistaken in ACC 2 as a starting symbol. 1 il.

Description

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The invention relates to telecommunications and can be used for asynchronous matching of discrete signals with a synchronous digital path.

The purpose of the invention is to increase the reliability of the reception.

The drawing shows a structural electrical circuit of the proposed device.

The device for receiving discrete signals comprises a drive 1, an analyzer 2 code combinations, a sensor 3 of code sequences, a 4-slot converter and a trigger 5.

The device works as follows.

The clock mode of the device for receiving discrete signals is specified by the clock frequency input to the sensor 3 of the code sequences, the output of which forms three code sequences K |, Kg, Kz, their follow-up period is, respectively .t, 2t, 4t, where t - the duration of the code zone (or the sampling period). The Kz and Kz code sequences define the binary code of the zone number: 00-1 zone, 01-11 zone, 10-III zone, 11 - IV zone. The Kz sequence is also the synchronous digital path clock sequence ().

The discrete signal transmitted by the sliding index method with confirmation is fed to the input of accumulator 1, which contains a four-bit serial-parallel register (not shown). In synchronous digital path ticks, code symbols are written to register 1 of storage. RI-R4 signals go to analyzer 2 of code combinations, which control the content of the last two bits of drive 1 (i.e., Rs and R4). A mismatch between signals R3 and R4 means the arrival of start symbol A to the third bit of register 1 of a drive. In this case, a control signal Z is generated in the analyzer of 2 code combinations, which also goes to the (control) fifth input of the converter 4, the number - interval. Since, at a given time, the starting character A is recorded in the third register bit, then the second and first bits of the register 1 of the accumulator 1 contain the qualifying symbols 62, and B ,. The signal Z in the analyzer 2 code combinations records the symbols B9 and B into its first pair of memory cells (not shown). At the same time, the symbols Ba and BI of the transmitting code combination previously recorded in the first pair of memory cells are rewritten into the second pair of memory cells of the analyzer 2 code combinations, where the analysis of the numbers of the previous and received code combinations is carried out. If the zone number of the incoming code combination per unit (modulo four) is greater than the zone number of the previous code combination, the output of the analyzer is

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with

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With 2 code combinations, a zero signal A is generated. Otherwise, signal A has a single value.

The signal Z, coming from the analyzer 2 code combinations to the input of the converter 4 number - interval, turns it on. From this point in time in converter 4, the number-interval begins comparing the code sequences Ki, K2 and Kz with the signals., R2 and Ra, respectively.

In accordance with the specified method of coding zone numbers with and simultaneous pairwise matching of signals K, R2, R3 with Ki, K2, Kz will occur in the first zone, with and R3 1 - the second, with R2 1 and R3 1 - in the third, with R2 1 and R3 1 - in the fourth. Moreover, at KO, coincidence occurs exactly in the middle of the code zones, and at X, 1 - at their beginning. Thus, at L 1, the front of the discrete signal is shifted by an amount, i.e. half the duration of the code zone.

The reconstruction of the fronts of a discrete signal is performed using trigger 5, to the information input of which a discrete input signal is applied, and to the sync input - a signal from the information output of the converter 4, the number is an interval.

At the same time, at the moment of recovering the front of a discrete signal in the 4-interval converter, a control signal is fed to the drive 1. This signal in drive 1 records the first, second and fourth bits of the register of drive 1 and writes the value of the start symbol. And those. signal from the third bit of the register. This is necessary so that the qualifying symbols are not perceived in the analyzer 2 code combinations as a starting symbol. Further operation of the device is similar.

Claims (1)

Invention Formula A device for receiving discrete signals containing a drive, the first and second outputs of which are connected respectively to the first and second inputs of the converter number — the interval, the first output of which is connected to the first input of the trigger, the output of which is the output of the device whose signal input is the first input of the drive , characterized in that, in order to increase the reliability of reception, a code combination analyzer and a code sequence sensor are introduced, the first output of which is connected to the third input of the pre Former number - interval and with the second input of the drive, the first, second, third and fourth outputs of which are connected so1401633 34 responsibly to the first, second, third expensively connected to the second trigger input to the fourth input of the code analyzer, with the sixth and seventh inputs of the precombinations, the first and second outputs of which form the number - spacing of the connector are connected respectively to the fourth and fourth respectively to the second and third and by the fifth inputs of the converter, the number -s to the outputs of the sensor of the coded sequence interval, the second output of which is connected to the system, the input of which is the clock input of the third drive, the first input by the code device.