SU1338101A1 - System for transmitting and receiving information in recurrent sequences - Google Patents

Abstract

This invention relates to a technique for transmitting discrete information and provides improved noise immunity. The system contains on the south- side of the element And 1, RS-trigger 2 control, decoder 3, the main r. 1 4- Transmitted {information Request from / - Formo: 4 and forward Starting the transfer End of the transfer W 4711 iLr G 7Lat Stu (L from co 00 nowenffiff (b (/

Description

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modulo two adders, 4, transmitting p-bit shift register 5, pulse generator 6, elements OR 7, 8, n-channel multi- I typelexer 9, RS mode trigger 10 transfer mode, 11-cycle counter, edge selector 12 , additional block 13 modulo-two adders, a decoder 1A of the zero state of the register, and on the receiving side - a demodulator 15, n-bit shift register 16, the main receiving unit 17 of the modulo-two adders, receiving decoder 18

one

The invention relates to a technique for transmitting discrete information and can be applied for the session transmission of discrete information.

The purpose of the invention is to improve the noise immunity of the system.

A schematic electrical system diagram is presented on the chergo.

CHL; heme transfer and reception of information recurrent 1ml sequences C (ds-neigh on the transmitting side element 1 AND, QW-trigger 2 control decoder 3, the main unit 4 modulo two adders, transmitting bits of the shift register 5 shift 6 pulse pulses, the first the element OR 7, the second element OR 8, the n-channel multiplexer 9, the RS flip-flop 10 of the transmission mode, the counter 11 cycles, the front selector 12, the additional unit 13 modulo-two adders and the decoder 14 of the zero register state, and on the receiving side - demodulator 15, n-bit shift register 16, main receiving unit 17 modulo-two adders, receiving decoder 18 terminal phase-start combination, counting counter 19, RS reception trigger control RS-20, reception mode switching RS-trigger 21, modulator 22, modulo element II 23, element OR 24, additional receiving unit 25 modulo-two adders, block 26 keys, decoder 27 combination of information transfer termination, three-terminal phase-start combination, counting counter 19, RS- receiving mode control trigger 20, RS switching trigger 21 and type of reception, modulator two adder 22, element I 23, RSHI element 24, additional module modulo-receiver two, modulators two, key block 26, decoder 27 combination of the end of transmission of the informer, three-channel multiplexer 28, front selector 29, counter 30 cycles and two-channel multiplexer 31. 1 Il.

B1 multiplexer 28, front selector 29, 30 cycle counter and two-channel multiplexer 31., The system works as follows ..

In the initial state on the transmitting side, the RS trigger trigger 2 is in the zero state, which provides a signal to its

an inverse output, which, by the installation R-output, holds the RS flip-flop 10 of the transmission mode directly, and the transmitting p-bit shift register via the first element OR 7

in the zero state. In this case, the signal from the inverted output of the RS flip-flop 10 of the transfer mode ensures that the counter of 11 cycles is kept in the zero state and the channels X of the n-channel multiplexer 9 are turned on. The zero state of the transmitting n-bit shift register 5. is decoded by the decoder 14, the signal from the output of which, at the same time, it enables switching on of the parallel recording mode on the P / S input of the control of the recording mode of the transmitting p-discharge register 5 of the shift. By switching channels X to a p-channel multiplexer

9, a connection is made to the U-input of the sequential recording of the transmitting p-bit shift register 5 of the main unit 4 modulo-two adders and to the D-inputs of the transmitting

n-bit register 5 shift signal from the inverse output to the RS-flip-flop

.

10 transfer mode. The clock pulses coming from the clock register input 5 and the counting clock input C of the counter 11 cycles clock pulses from the generator output 6 clock pulses do not cause them to work because of the presence of a signal at their installation R inputs. The described state is preserved until the signal with input Start transmitting the transmitting part. At the receiving side, in this case, the RS control flip-flop 20 and the RS switching flip-flop 21 are also in the zero state. The signal from the inverse output of the RS flip-flop 20 provides switching on the channels X of the two-channel multiplexer 31, and the signal from the inverse output of the RS flip-flop 21 enables the channels X of the three-channel multiplexer 28 and sets and keeps the counter of 30 cycles in the zero state. Switching on channels X of a three-channel multiplexer 28 provides a connection to the J-input of the second channel of a two-channel multiplexer 31 and to the input of adder 22 modulo two outputs of the main receiving unit 17 modulo-two adders, to the installation S-input of the RS flip-flop 20 of the main output of the counter 19 credits segments and to the Y-input of the first channel of the two-channel multiplexer 31 output receiver decoder 18 terminal combination of the phase start. Switching on channels X of a two-channel multiplexer 31 provides connection of the J-input of the sequential recording of the receiving p-bit shift register 16 to the output of the Synchronous demodulator Bit 15 via the second channel of the two-channel multiplexer 31 and disconnecting the installation R- and S-inputs, respectively, RS-flip-flops 20 and 21 on the first channel of the multiplexer 31. Thus, the transmitting part is prepared to transmit information, starting with the transmission of the phase-start signal, and the receiving part - to receive information that begins with the transmission phase start signal.

The process of information transfer begins with the arrival of the signal from the input. The beginning of the transmission of the transmitting part, this sets the RS-flip-flop 2 of the control on S-trigger and disconnects the operation of the transmitting n-bit register of the 5 shift by removing the holding signal from it.

I o I

R-in. Under dGH .pchum psrnpc) of the output pulse from the generator, 6 such pulses in the register bits are made parallel recording of the initial conditions of the recurrent phase-start sequence. The initial conditions are set by supplying the corresponding D-BXO bits of the register 5 with the inverse output of the RS flip-flop 10 through the X-channels of the n-channel multiplexer

9 and a signal to the P / S input of register 5. Following subsequent pulses from generator 6, the peKyppeHTHofi symbols of the phase-start sequence are generated. The nature of the recurrent phase-start sequence is determined by the corresponding connection of the adders in modus two blocks of 4 modulo-two adders and the corresponding connection to the outputs of the bits of the shift register 5. The transmission process of the phase-start sequence lasts until the end of its period. At the time of the end of the period of the phase start-up sequence at the output of the decoder 3, a signal is generated, which, through element I 1 and the PKI element 8, goes to the request for information on the transmission of the transmitting part, the installation S-response RS-Tpni-repa

10 and through an element) p-lUlU 7 to the setup R-input of register 5. RS-flip-flop 10 under the control of this signal switches, which makes it possible to turn on the Y channels of the multiplexer 9. Register

5 is set to the zero state, which provides at the P / S input from the output of the decoder 27 a signal for switching on the parallel recording mode to the register 5.

The signal Request information to the inputs The transmitted information of the transmitting part is supplied with the values of the combination of the transmitted information. In practice, this can be done either from a start-stop transmitter or from a drive in the form of a buffer memory. Signals from the inputs The transmitted information through the corresponding Y-channels of multiplexer 9 is fed to the D-inputs of the bits of the shift register 5. The Y-input of the sequential write register 5 through the first channel of the multiplexer 9 receives signals from the output of the block 13 modulo-two adders. Under the action of the next clock pulse from gemsratopa 6, 5 values of the transmitted information are recorded in the register as initial conditions of the M-sequence, written in accordance with feedbacks specified by the modulo adders connection, two modulo-13 adders, and connecting to the corresponding outputs of the bits of the register 5 shift. By removing the holding signal from the R input of the 11-digit counter, when the KZ-tripler 10 is installed, the counter 11 starts counting the pulses arriving at its counting C | V input from the generator 6. The capacity of the counter 11 cycles is set to one more than the number of bits M -consistent. with and. The transfer of the M-sequence values occurs before the appearance of a network at the output of the counter 11, the front of which is highlighted by the front selector 12. The signal from the edge selector 12 through the OR element 7 sets the shift register 5 shift to nullios and goes to the output Request and the information to the transmission of the transmitting side, when the installation takes place additionally to the RS-ipHjTcpa 10 input. Processes p lit. recsSch of the ch.tn during the transmission of the second of the following and subsequent K (1mbi1 tions of protec- tions ta / kc, klk h njiH the transmission of the first combination. Head (the transmission r = x / i is transmitted) 11,111) of the combination of the end of the transmission by the request signal and the signal to the end End of the transmission but to the signal A request for information on the transmission following the transmission of the combination of the end of the transmission,

The signal is transmitted to a synchronous demodulator 15, which performs the selection of the values of the parcels of the received signal. In the process of demodulating the values of the parcels at the output of the demodulator bit, the sowing signals are formed that are synchronous with the signals at the output of the tact of the demodulator 15.

Signals from the output of the demodulator bit 15 are received via the second channel mule)) Tiplexer 31 to the 3rd input of the serial register of the receive register 16. Signals from the output of the clock of the demodulator 15 record the values of the demodulated signal to the bits of the register 16. The main receive is the Hbrfi block 17 modulo-2 adders according to signal values

five

0

The signals recorded in register 16 produce signals that are communicated through the first channel of the three-channel multiplexer 28 and are compared with the values of the 1 H1 analog pitch signals in the adder. 22 modulo two. If there are no distortions in the communication line, after filling all the bits of register 16 at the output of the main receiving unit 17, the signal values will correspond to the values of the demodulated signals at the output of the demodulator bit 15. This is due to the fact that -. Indental units 4 and 17 modulo-two adders and their points of connection to the outputs of register bits 5 and 16 were used on each side. When the signals from the BIT output of the demodulator 15 and the modulo-17 block 17 coincide, there is no signal at the output of the adder 22 modulo two, which leads to the prohibition of the passage of signals from the output of the clock of the demodulator 15 through the element AND 23 and the element OR 24 to the installation R-input of the counter 19 of valid segments, the counter 19 starts counting signals

; () Tact, sent to his counting C-input from output TaKi of demodulator 15, marking the number 1), 1x without distortion of the river-sequence sequence of phase zusk. The capacity of the counter 19 but the main output is selected from the condition of providing the phase start required from the false reception. The error-free reception of consecutive bits of a recurrent phase-start sequence in a number equal to the volume of the counter of 19 valid segments is accompanied by the formation of a signal. Np at its output. False accumulations of signals in counter 19 are

5 is due to its installation. By the R-in. At Ka; tu; oM the signal does not match at the inputs of modulator 22 modulo two. The signal from the output of the counter 19 through the second channel of the three-channel multiplexer 28 is fed to the installation S-BSK RS-trigger 20.

When switching the RS flip-flop 2U, the Y channels of the two channels are turned on.

5 multiplexer 31, through

the second channel Nr / of the multiplexer 31 switches the J-input of the register 16 from the output of the Bit of the demodulator 15 to the input of the block 17 of adders per module

0

0

7 133 two, and through the first channel of the multiplexer 31 - connecting the installation R- and S-inputs, respectively, R.S-third of 20 and 21 to the output of the decoder 18. From this point on, the register 16 operates in an autonomous mode of generating a recurrent phase-start sequence in accordance with

feedbacks of their outputs through the y M-sequence, coinciding with

20

thirty

block 17 modulo adders. By sending a signal from the direct output of the RS flip-flop 20 through the OR element 2A to the installation R input of the counter 19, the latter is set and held in the zero state. The operation of register 16 in the autonomous generation mode of the recurrent phase-start sequence continues until the end of the sequence period, and a combination is set at the outputs of register bits 16, which is decoded by the decoder 18 by a signal at its output. The signal from the output of the decoder t8 through the third channel of the multiplexer 28 and the first channel of the multiplexer 31 goes to the installation R- and S-inputs, respectively, of the RS flip-flops 20 and 21. Installing the RS-flip-flop 20 on the R-input causes the channels of the multiplexer 31 to switch and remove the signal from the set K-input of the counter 19. Setting the RS-flip-flop 21 to the S-input turns on the channels of the multiplexer 28 and removes the signal from the setting R-input of the counter 30 supplied from the inverse output of the RS-flip-flop 21. Switching the multiplexers 31 and 28 results to the next. Through the first channel of the multiplexer 28, the output of the additional block 25 of adders modulo two is connected to the Y-input of the channel of the multiplexer 31 and the input of the adder 22 modulo two, through the second 45 channel of the multiplexer 28 additional Hbrfi the output of the counter 19 is connected to the installation S-input RS- the trigger 20, and the output of the counter 30 through the edge selector and the third channel of the multiplexer 28 is connected to the Y input of the first channel of the multiplexer 31. These switchings provide the established synchronization with the M-sequence transmitted after edachi recursive sequence phase starting. If the received bits of the M-sequence are not distorted, then after filling all

accepted, In this case, the counter 19 begins to record the reception of the credited segment of the M-sequence. The capacity of the counter 19 for the additional output is set to the length over an even segment, determined from the conditions for providing the required interference to the stability of information reception. From the moment of switching the RS flip-flop 21, the counter 30 counts the clock pulses arriving at its counting C input from the output T of the demodulator 15. The capacity of the counter is equal to the M-sequence period, which is ry one time. After taking the credible segment of the installed length at the additional output of the counter 19

It also sends an RS-Trig-grr 20 via the S-input. From this moment, the reg-controller 16 generates an M-sequence autonomously until the end of its period and setting the value corresponding to the first clock j of the M-sequence. At the same time, a signal appears at the output of the counter 30, the front of which is allocated by the front selector 29. The output signal from the front edge selector 29 is fed to the output, permission to receive the receiving side information, the control input of the key unit 21 and the setting R and B inputs, respectively, RS flip-flops 20 and 21.

Changing the initial conditions for generating the M-sequence leads to cyclic permutations of this sequence. This property is used in the transmission of information, with each combination of information corresponding to the transfer of the same M-sequence with the shift corresponding to this combination. When received by writing to the register 166 of the shift of the values of the received M-sequence and identical connection points of the same blocks 13 and 25 modulo-two adders respectively to registers 5 and 16 about 50

eight

Bit regs 1 Id riyi: 1L11isi reg Istr 16 zipchoiiG 11a-chr c (1n M-sequence, received from the output Vit dsmododorl 15nl J-input register 16 draw ptorei clln multiplexer 31, at the output of an additional unit 25 cyM faTopoH modulo two bit values are generated

accepted, In this case, the counter 19 begins to record the reception of the credited segment of the M-sequence. The capacity of the counter 19 for the additional output determines the length of the test segment, determined from the conditions for ensuring the required noise immunity of information reception. From the moment the RS flip-flop 21 is switched, the counter 30 counts the clock pulses arriving at its countable C input from the output T of the demodulator 15. The counter capacity is chosen equal to the M-sequence period, which is ry one time. After taking the credible segment of the installed length at the additional output of the counter 19

thirty

 15 45

It also sends an RS-Trig-grr 20 via the S-input. From this moment, the reg-controller 16 generates an M-sequence autonomously until the end of its period and setting the value corresponding to the first clock j of the M-sequence. At the same time, a signal appears at the output of the counter 30, the front of which is allocated by the front selector 29. The output signal from the front edge selector 29 is fed to the output, permission to receive the receiving side information, the control input of the key unit 21 and the setting R and B inputs, respectively, RS flip-flops 20 and 21.

Changing the initial conditions for generating the M-sequence leads to cyclic permutations of this sequence. This property is used in the transmission of information, with each combination of information corresponding to the transfer of the same M-sequence with the shift corresponding to this combination. When received by writing to the register 166 of the shift of the values of the received M-sequence and identical connection points of the same blocks 13 and 25 modulo-two adders respectively to registers 5 and 16 about 50

91338101

The synchronization of the local 16 M-consistency generated by the register 16 with the received one comes down.

Synchronization of sequences ensures the formation at the outputs of register register 16 in the first clock interval after the last interval of the period of the M-sequence of the combination of the initial conditions from which the M-sequence was generated on the transmitting side. Counting of intervals equal to the M-sequence period increased by one is provided by counter 30. Consequently, at each time the front is selected by the front selector 29 from the output of register bits 16 through the block 26, the receiving side receives a combination corresponding to combinations of information transmitted. The signal from the output of the edge 29 through the third channel of the multiplexer 28 and the first channel of the multiplexer 31 sets the R-input of the RS flip-flop 20 and confirms the S-input of the RS flip-flop 21. Switching the RS flip-flop 20 causes the X to turn on canon multiplexer 31, which translates the receiving unit, c) beginning to receive the next information. Receiving the next xc combination of information proceeds in a manner similar to receiving the first combination of information after the start phase. The process of receiving information is completed upon receipt of a transfer completion pattern. This combination is decrypted by the decoder 27, and the signal from its output sets RS-flip-flop 21 on R-input. Switching RS-flip-flop 21 enables the X channels of multiplexer 28 and sets and holds on the R-input of counter 30. The indicated switches are BOD to receive section in the mode of reception of the phase-start signal, after the reception of which the new reception of information becomes possible.

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Claims (1)

Invention Formula A system for transmitting and receiving information by recurrent sequences, containing on the transmitting side an RS-control trigger, whose Z input is the input of the signal Start of transmission, and the R input is the input of the signal The end of transmission, generator 101 ten clock pulses, the output of which is connected to the C input of the transmitting n-bit shift register, the outputs Which is connected to the inputs of the block of adders modulo two and the decoder, the output of which is connected to the first input of the element I, and on the receiving side an RS-trigger of reception mode control, an RS-trigger of switching the type of reception, modulo two, element AND, element OR , counter of credits, demodulator, the input of which is the input of the receiver On the 5th side, the clock output is connected to the Gamma of the p-bit shift register, the outputs of which are connected to the inputs of the receiving unit of modulo two adders and the receiving decoder end 0 combinations, distinguishing so that, in order to increase but from the noise side five 0 D) 0 five 0 55 stability, an additional unit modulo two and a zero state decoder are entered on the transmitter, to the inputs of which are connected the inputs of the main unit of modulators two, the output of which is connected to the X, -input of the entered p-channel multiplexer, to Y, - the input of which is connected to the output of the additional block of modulators modulo two, the first element {SCHI, the second element of SLI, the first input of which is connected to the output of the element I, connected in series to the cycle counter and the front edge divider, the output of which is connected n to the second input of the second OR element, the output of which is connected to the S input of the entered RS flip-flop of the transfer mode and the first input of the first OR element; (the second input of which is connected to the RS output of the control trigger and the trigger input of the transmit mode, whose S input is Input The request for information on the transmission, and the direct and inverse outputs are connected to the control inputs of the n-channel multiplexer, the (X-1) inputs of which are connected to the inverse output of the RS-flip-flop of the transmission mode, the (Y-1) inputs are Inputs The output is output by the transmitting side and connected to the L input of the transmitting p-bit shift register, to the D-inputs of which are connected (n-1) -e outputs of the n-channel multiplexer, to the input the output of the first OR element is connected, and connected to the R / S-input the output of the zero state register decoder, with this second input of the And element and the R input of the cycle counter are connected to the inverse output of the RS flip-flop of the transmission mode, and the S input of the cycle counter is connected to the output of the clock generator, and an additional a receiving unit modulo-two adders, a block of keys, a decoder for combinations of the transmission of information, the output of which is connected to the R input of an RS flip-flop for the type of receiver, ten The outputs of the RS flip-flop for the receive mode, the S input of which is connected to the first output of the two-channel multiplexer and the R input of the RS flip-flop of the receiving mode control, the inverse and direct outputs of which are connected respectively to the first and second control inputs of the two-channel multiplexer and through the element OR with the R-input of the counter of credited segments, the C-input of which is connected to the first, the second and third outputs of the three-channel multiplexer are connected respectively to the Yj-output of the double-side demodulator output and the C-input of the counter cycles, R-input of which is a three-channel and sub-channel is multi-key A to the inverse output of RS-trig- plexor serially connected ger shift form the reception and the loop counter and the front extractor, the output of which is connected to the first input key unit, the output of which connected to the inputs of the decoder of the common multiplexer and the first input of the end of the transmission and is the modulo two adder's house, the second outputs of the receive signals whose combination and X are the two-channel input, to the Yj input of the three-channel multi-channel the multiplexer is connected to the elevator and is the output of the signal to the demodulator bit, the 3-input 25 RS-triggers to control the receive mode and Y, the input of the two-channel multiplexer, the second output of which is connected to the J input of the n-bit shift register, the outputs of which are connected to receive information, while the output of the main receiving unit is connected to the X input of the three-channel multiplexer modulo-two adders, to Y (-input - output of the additional receiving unit of zonen-adders with inputs of the auxiliary module; two; to and Yj inputs - outputs of the counter of valid segments, to the XZ-INPUT - output of the receiver decoder phase combinations start, and control inputs are connected and, the second input of which is connected to the direct and inverse-clock output of the demodulator, respectively. Editor A. Ogar Compiled by I. Gracianska Tehred I.Popovich Proofreader L.Reskid Order 4148/58 Circulation 638 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 The outputs of the RS flip-flop for the receive mode, the S input of which is connected to the first output of the two-channel multiplexer and the R input of the RS flip-flop of the receiving mode control, the inverse and direct outputs of which are connected respectively to the first and second control inputs of the two-channel multiplexer and through the element OR with the R-input of the counter of credited segments, the C-input of which is connected to the first, the second and third outputs of the three-channel multiplexer are connected respectively to the Yj-output of the double-side demodulator output and the C-input of the counter cycles, R-input of which sub key A to the inverse output of RS-trig- ger shift form reception, and modular two, the second input of which and the X input of the two-channel multiplexer are connected to the output of the demodulator bit, the 3 input module of adders modulo two and key block, and the output of the modulo two adder is connected to the second input of the element OR through the element