SU1297230A1 - Method of coding signal with partial response for digital information transmission - Google Patents

Abstract

The invention relates to computing. Its use in digital information transmission systems through intersymbol interference channels improves noise immunity. The method consists in encoding each zero character of the input code with a duration equal to the cycle T, changing: the level of the two-level signal in the average cycle and encoding the single characters of the same duration with the constant level of the two-level signal. By replacing these signals when transmitting long sequences of ones or zeros with signals with a special law of changing the level of a two-level signal, the distortion is reduced due to low frequency intersymbol interference and self-synchronization is provided at the reception. 1 hp f-ly, 6 ill. (L with so with so about

Description

The invention relates to computing and can be used with / 1 in systems for transmitting digital information through channels with intersymbol interference,

The purpose of the invention is to improve noise immunity.

FIG. 1 shows timing diagrams for the case n fK, w 5K + 2, which coincides with the prototype method; in fig. 2 is the same for the case in FIG. 3 and 4 - timing diagrams of possible options for the transfer of a sequence of units (a) or zeros (b); in fig. 5 and 6 are block diagrams of a coding and decoding device, respectively, with which this method can be implemented.

The coding principle of this method consists in the destruction in the transmitted signal of long sequences of ones or zeros while maintaining the basic property of the signal with a partial response (. Or a duo-binary code) —high specific transmission network speed.

The coding is performed as follows.

If in the input signal (Fig.) There are no sequences of symbols О of length K + 3 or more clock intervals and a sequence of symbols 1 of length K + 1 or more clock intervals, then the formation of the transmitted signal is carried out according to the rule of forming a duo-binary code. In this case, each symbol O of the input signal (Fig. IQ.) Corresponds to a change in the level of the output signal, while with symbols 1, the change in the level of the output signal is not made (Fig. LS). At the output of a channel having a bandwidth if d1 / 2T (T is the duration of the clock interval of the transmitted signal) in this case, a signal is generated, which is shown in FIG. 1b. Intermediate level: The shade of this signal corresponds to the symbols On the initial information, and the boundary levels (+1 or -1) correspond to the symbols 1.

For sequences of symbols 1 with the number of symbols, the output signal is formed according to the following rule (Fig. 3A): first, the entire sequence of length n symbols 1 is divided into blocks of K clock intervals in each block. The length of the last block depends on

the values of K and can vary from 1 to K. Then, in all blocks except the last, the signal level is changed K times, starting from the middle of the second to the middle of the last clock interval inclusive, In the last block, for any ratios n and K, the signal level is not is changing.

The signal shaping rule for the character sequence O with the number of symbols is illustrated in FIG. 3S. First, the entire sequence of symbols O of length m of clock intervals is divided into blocks by K + 2 symbols O, the length of the last block depends on the ratio of the values of m and K and can vary from 1 to clock intervals. Then, in all blocks except the last, the K + 2 signal level is changed, starting from the middle of the first to the middle of the last but one (K + 1) -th clock interval. In the last block, for any ratios between the values of m and K +, the change in the signal level is carried out according to the rule of forming a duo-binary code.

FIG. 2 shows a variant of coding according to the proposed method with, when in the initial information there is a series of characters 1 with a number and a series of characters O with a number.

The signal with the described properties can be obtained in different ways. For example, in the first embodiment (Figures 2 and 3, the signal is generated at a frequency that is a multiple of the half-clock frequency of the input signal. In the second version (Fig. 4), when K and K + 2 changes, the signal levels are repeated at a frequency that is not a multiple of half-clock input signal frequency. With both coding options, the signals are generated that do not differ in shape.

Recovery of the original binary information at the reception can be carried out according to the following rule:

the section of the signal with an intermediate level between pulses with different boundary levels, having a length equal to (K-1) -th clock interval, corresponds to symbols 1 of the initial digital information; other signal sections with intermediate level correspond to symbols

the pulse of a signal with one of the boundary levels corresponds to the symbol O of the original digital sequence, if the level of this pulse is opposite to the level of the preceding pulse and the pulses are separated by (K + 1) -th clock interval; all other pulses correspond to the symbols 1.

The K parameter is selected based on a number of conflicting signal requirements and is determined by the characteristics of the particular transmission channel. L Smaller K values lead to an increase in the number of level changes in the received signal. This increases the stability of the acquisition timing system and reduces signal distortion 15 due to low-frequency intersymbol interference. Minimizing the K value is also desirable to reduce the error multiplication factor when decoding a signal. 20

However, at small values of K, a relatively large change in the pulse frequency of the transmitted signal is observed for sequences of symbols 1 and O, which 25 leads to a distortion of the duration and amplitude of the pulses of the received signal. In the worst case (at) at the reception, a 16% decrease in the aperture of the eye diagram is observed, which decreases by 30 with an increase in K.

The invention consists of the proposed sequence of operations over the input digital signal, in which the received signal 35 for symbol sequences 1 excludes the appearance of unipolar sequences with one of the boundary levels and limits the number of clock intervals without changing the 40 level of the received signal as for sequences characters 1. as well as sequences of symbols O. Thus, the low-frequency components are reduced in the signal and 45 provides the signal receiving system ala self-synchronization mode.

The specified positive effect

one of the boundary levels, corresponding only to those sections in the transmitted signal, within which the signal level changes less frequently than through one clock interval of the input digital sequence (Fig. 1 and 2). When using the proposed coding method, the length of portions of the transmitted signal without changing the signal level n can exceed K clock interval when transmitting 1 and K + 2 clock intervals when transmitting O symbols (Figs. 2, 3 and 4). Therefore, the level of no frequency components in the spectrum: the signal is smaller than when using the duobinary encoding method for which the length of the portions of the received signal with one of the boundary levels can increase indefinitely.

Self-synchronization mode at signal reception is provided by a stable adjustment of the synchronization system, since limiting the length of sections without changing the level at signal transmission corresponding to the sequences of characters 1 of the input digital signal guarantees reception of pulses following at least through K-1, and when transmitting sequences of symbols, O — not less frequently than K + 1 clock interval;

In practice, the division of a sequence of identical symbols into blocks is performed sequentially.

A coding device for implementing this method of generating a signal with a frequency not 1fat of the half-clock frequency of the input signal includes (Fig. 5) delay elements 1 2 for one clock interval first and second decoders 3, 4, delay element 5 for K + 2 clock intervals, elements 6, 7, elements 8, 9, first, second and third, shapers 10, 11, 12 pulses.

a delay element 2 for 2 clocks is achieved by forming an interval signal, RS-flip-flops 14, 15, an elela by the described rule and is based on the features of transmitting signals with a partial response, when the received pulse sequence is a superposition of the 1st transmission path responses to the transmitted signal in adjacent clock intervals. At the same time, in the signal with a partial response, pulse 1 is generated,

cop or 16, logical ko mutator 17 counting trigger 18,

The device decoding its signal (Fig. 6) includes comparators 19, 20, ele; - aents 11 21 - 24, RS - trigger 25, elements OR 26, 27, a block 28 for extracting the synchronization signal, a decoder 29 after the trigger from the boundary level, corresponding only to those sections in the transmitted signal, within which a change in the signal level occurs less frequently than after one clock interval of the input digital sequence (Fig. 1 and 2). When using the proposed coding method, the length of the portions of the transmitted signal without changing the signal level cannot exceed K clock intervals when transmitting 1 and K + 2 clock intervals when transmitting O symbols (Figs. 2, 3 and 4). Therefore, the level of low-frequency components in the spectrum: the signal is less than when using the duobinary encoding method for which the length of the sections of the received signal with one of the boundary levels can increase without limit.

The self-synchronization mode when receiving a signal is provided by a stable adjustment of the synchronization system, since limiting the length of sections without changing the level when transmitting a signal corresponding to the sequences of characters 1 of the input digital signal ensures that the following pulses are received at least through K-1, and when transmitting O symbols - not less often than K + 1 clock interval;

In practice, the division of a sequence of identical symbols into blocks is performed sequentially.

A coding device for implementing this method of forming a signal with a frequency not 1fat of the half-clock frequency of the input signal includes (FIG. 5) delay elements 1, 2 for one clock interval first and second decoders 3, 4, delay element 5 for K + 2 clock intervals, elements And 6, 7, elements 8, 9, first, second and third, shapers 10, 11, 12 pulses.

a delay element 13 for 2 clock intervals, RS-triggers 14, 15, an element OR 16, a logic set mutator 17, a counting trigger 18,

The signal decoding device (Fig. 6) includes comparators 19, 20, ele; - aents 11 21 - 24, RS - trigger 25, elements OR 26, 27, a block 28 for extracting a synchronization signal, a decoder 29 for sequence K-1 O , the decoder 30 of the sequence K + 1 character O, the shift register 31.

The coding device operates as follows.

When the K + 2 SIMEOL O sequence arrives at the input, a detection pulse of this sequence arrives at the output of the second decoder 4 with a delay of one clock interval, which arrives at the first input of the AND 7 element. The second input of this element AND 7 is connected through the HE 8 element with information input device coding. Due to the delay of the signal in element 1, the delay for one clock interval impulse at the input of element And 7 is formed only if at the input of the coding device, after a sequence of Ki-2 characters O, at least one more pulse O arrives. impulse output element And 7 it sets the RS-flip-flop 14 to the state 1, 25 puller 12 is carried out. The signal from the direct output of the RS-flip-flop 14 through the element OR 16 is fed to the control input of the logic switch 17 and connects to the output of this switch 17 output The second and third shaper 11, 12 pulses. At the same time, at the output of the second shaper 11 pulse 30

with a delay of one clock interval of the input digital signal with the help of the delay element 2, which ensures the change of the output signal level only from the second clock interval in blocks for K symbols 1 After starting the third generator, 12 pulses form its impedance pulses following frequency in K / (K-1) times the clock frequency of the input digital signal. These pulses through the logical switch are fed to the input of the counting trigger - Q pa 18, which forms the output signal

element And 7, a sequence of K + 2 pulses, following at a frequency, appears (K + 2) / (K + 1) times the clock frequency of the input digital signal. These pulses through the logical switch 17 are fed to the input of the counting trigger 18, which generates the output signal. A second pulse formaker 11 is launched once the second decoder has detected 4 K + 2 characters O before the appearance of at least one character at the device input. The appearance of this character causes the output of the RS flip-flop 15 to go to state O is carried out at the output of the element 5 of a delay of K + 2 45 clock intervals of the symbol O. For a sequence with n characters 1, a large and multiple of K and the signal level does not change in the last block of K characters 1

ment 5 delays at K + 2 clock in- 50 due to the impossibility of starting the third

a torrent appears that sets the RS flip-flop 14 to the state O. In this case, no matter how long the last block in the sequence of m symbols O has, the output of the logic switch 17 is disconnected from its third input.

When the RS flip-flop 14 is in the O state, it is possible to connect

the driver of 12 pulses, since there is no pulse of the signal at the first input of the element 6. At a value greater than and not multiple of K, 55 the signal level in the last clock intervals of the signal K after the block of characters 1 of the input information does not change due to the absence of a pulse the second input element and 6. When

72306

logical switch 17 to the first or second information inputs depending on the state of the RS-flip-flop 15. When the first decoder has 3 sequences K of characters at the input, after which the symbol 1 also appears, the trigger 15 is set T with a delay of two clock intervals, which is necessary to equalize the moments at which information appears at the information inputs of the logic switch 17. The delays are created by a delay element 13 of two clock cycles.

interval, and the pulse of setting the RS flip-flop 15 to state 1 is formed at the output of the element 6, and the output of the third pulse generator 12 is connected to the output of the logic switch 17, which is achieved by sending a signal from the direct output of the RS flip-flop 15 through the element OR 16 to the control input of the logic switch 17. A third pulse generator 12 is started.

thirty

with a delay of one clock interval of the input digital signal with the help of delay element 2, which ensures the change in the output signal level only from the second clock interval in blocks for K symbols 1. After starting the third generator 12 pulses, a sequence of K pulses is generated on its output following frequency, in K / (K-1) times the clock frequency of the input digital signal. These pulses through the logical switch 17 are fed to the input of the counting trigger - Q pa 18, which forms the output signal.

The RS-flip-flop 15 is set to the state O when the output of the element 5 appears at a delay of K + 2 45 clock intervals of the symbol O. For a sequence with a number n of symbols 1 greater than and multiple to the value of K, and the signal level changes in the last block K characters 1 not produced

50 due to the inability to start the third

the driver of 12 pulses, since there is no pulse of the signal at the first input of the element 6. At a value n greater than and not a multiple of K, 55 the signal level in the last clock intervals of the signal K after the block of characters 1 of the input information does not change due to the absence of a pulse the second input element and 6. When

values of n K, setting the RS-trigger 15 to state 1 with the launch of the third driver 12 pulses does not occur due to the lack of a signal at one of the inputs of the And 6 element.

When the RS-flip-flops 14, 15 are in the O state, the output of the logic switch 17 is connected to the output of the first pulse shaper 10, which generates pulses corresponding to the O symbols of the input information 20

nation. The clock pulse interval is equal to the clock interval of the input digital signal. When connecting the input of the counting trigger 18 to the output of the first shaper 10 pulses, the change in the output signal level is carried out according to the rule of formation of the duo-binary code.

In the decoding device (FIG. 6), the input signal is fed in parallel to the inputs of the first and second comparators 19, 20, in which it is assumed that there is a signal with a partial response in the analyzed clock interval. At the output of comparator 19, a signal appears when pulses are detected

element 24 receives a signal from the output of the decoder 30, as a result of which a pulse appears at the input of setting the symbol O in the first cell of the shift register 31, and the symbol O is written into this cell. 10 In the case of the input of the device through K + 1 the clock interval of the pulse. with the upper boundary level, the character O is recorded in the first memory cell of the shift register 31 in the same way, but the pulse from the output of the comparator 19 enters the input of the AND 24 element through the AND 21 element and the OR 27. Later on device input them pulses that are separated by the (K + 1) -th clock interval and which have different levels, the process of writing the symbol O in the first memory cell of the shift register 31 is repeated similarly.

When pulses with different boundary levels appear at the device input, provided that these pulses

with the upper boundary level, and you are divided by the (K-1) -th clock interval of the comparator 20 - with the lower edge, the signal at the output of the decoder 30 is at the same level. With the appearance of a pulse sequence K + 1 character O

At the output of the comparator 19, the RS flip-flop 25 is set to state 1 and the signal from the direct output of this flip-flop is fed to the first input of the element AND 22. The same pulse through the OR 26 element is fed to the input of the decoder 29 of the K + 1 sequence O the decoder 30 of the K + 1 character sequence 0% of the input of the sync signal extraction unit 28 and is written into the first memory cell of the shift register 31,

35

40

is absent, but a pulse is formed at the output of the decoder 29. At the same time, 5puls from the output of the OR element 27 passes through the AND 24 element and enters the input of the installation of characters

one

in the first To the cells of the memory of the shift register 31. In the first cell of the memory of this register is written the symbol 1, and in the next one; K-1 cells O are replaced by symbols 1. As a result, the decoder restores

containing. K + 2 memory cells. Sell-45 sequences of stvolva 1 s information on the shift register 31, in the decoder 29 of the K-1 sequence of the symbol O and the decoder 30 of the sequence of K + 1 of the symbol O is performed by the clock signal from the output of the block 28 of the allocation of the synchronization signal. When the device enters the device through (K + 1) -th clock interval after im50

number of characters. For input signal pulses with the same boundary levels, separated by (K + 1) -m or (K-1) -th clock intervals, set the symbol O or -character

1 in the first cell and c1-1vol 1 in the next K-1 cells of the shift register 31 does not occur due to the lack of a signal at the inputs of the element with the upper boundary level, OR OR 27 (when the pulse reappears with the lower boundary damage - a pulse at the output of the comparator 19 is formed at the output of the comparator 20; there is no signal at the second signal, which after the passage of the element 21, and when repeated at the element AND 22 and element 27 or 27, the pulse at the output of the comparator enters the first input element And 24 and sets RS-three ger 25 put on January 1 e

 ABOUT

At the same time to the second entrance

element 24 receives a signal from the output of the decoder 30, as a result of which a pulse appears at the input of the character O in the first cell of the shift register 31, and the character O is written to this cell. In the case of the input of the device through K + 1 clock the upper pulse level interval. The character O is written to the first memory cell of the shift register 31 in the same way, but the pulse from the output of the comparator 19 enters the input of the AND 24 element through the AND 21 element and the OR 27 element. impu devices The pulses, which are separated by the (K + 1) -th clock interval and which have different levels, the process of writing the symbol O in the first memory cell of the shift register 31 is repeated similarly.

is absent, but a pulse is formed at the output of the decoder 29. At the same time, 5puls from the output of the OR element 27 passes through the AND 24 element and enters the input of the installation of characters

one

in the first To the cells of the memory of the shift register 31. In the first cell of the memory of this register is written the symbol 1, and in the next one; K-1 cells O are replaced by symbols 1. As a result, the decoder restores

string sequences of 1 s

number of characters. For input signal pulses with the same boundary levels, separated by (K + 1) -m or (K-1) -th clock intervals, set the symbol O or -character

1 in the first cell and c1-1vol 1 in the next K-1 cells of the shift register 31 does not occur due to the absence of a signal at the inputs of the element OR 27 (when the pulse reappears at the output of the comparator 19, there is no signal at the second input of the element And 21, and when the pulse is repeated at the output of the comparator 20, at the first input of the element (22). In other cases, the installation does not occur due to the absence of a signal at the outputs of the decoder 29 and 30.

Thus, this method without introducing redundancy, switching to multilevel signal transfer and introducing block synchronization at the reception provides increased noise immunity at a high specific data rate of digital information based on the reduction of signal distortion due to low-frequency inter-symbol interference and receiving self-synchronization at the reception.

Claims (2)

Claim 1. Method of coding a signal with , 1,2 .., starting from the middle of the second to the middle of the K-th cycle, is carried out by changing K times the level of the two-level signal, then the condition (p – K) is checked and, if it is fulfilled, the described procedure J-1 times (j 1,2 ...), until the condition (n-jK) ceases to be fulfilled, after which The 10 remaining intervals of duration (n-jK) leave the level of the two-level signal unchanged, encoding a sequence of m zero symbols of length tT for the case 15 from the middle of the first to the middle of the (K + 1) th cycle, the K + 2 times the level of the two-level signal is changed, after which the condition t - (K + 2) -T (K + 2) T is checked and, if so, With a partial response for transmitting digitization, the described procedure information is repeated, which is to be found once (, ...), until each zero character is added to the condition mZ (K + 2) J T (K + 2). T not cease to be performed, after which in the remaining interval the duration varies in the middle of a clock, and the code m-I (K + 2) l.T (). T changes the leveling of the single symbols of the length of the two-level signal in the middle of each clock. 2. The method according to claim 1, which is different from the fact that the changes in the level that, in order to increase the noise tolerance of the two-level signal, the performance, the coding sequence, if the conditions are met, carry n single characters of the duration (n-jK) or m-T (K + 2) T (K + 2) - T, by the nature of pT, for the case duration equal to the beat T, two-level signal, the level of which T is a two-level signal, the level of which does not vary within the cycle, differing in that With the aim of increasing the noise produced at intervals from T / 2 to T., Г О11ОООООО1О7 711 7 О О 7 7 О. , 1,2 .., starting from the middle of the second to the middle of the K-th cycle, is carried out by changing K times the level of the two-level signal, then the condition (p-K) is checked and, if it is done, the procedure described is J-1 times (j 1,2 ...), until the condition (n-jK) ceases to be fulfilled, after which the remaining interval of duration (n-jK) leaves the level of the two-level signal unchanged, encoding a sequence of m zero symbols of length tT for the case  from the middle of the first to the middle of the (K + 1) th cycle, a change in the K + 2 times the level of the two-level signal is carried out, after which the condition t- (K + 2) -T (K + 2) T is checked the signal carried out in the case of (n-jK) or t-T (K + 2) T (K + 2) -T, produced at intervals from T / 2 to T., VX Phie. 7 N- Compiled by O. Revievsky Editor N. Shvyschka Tehred A. Kravchuk Proofreader A. Obruchar Order 795/61 Circulation 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4