SU578648A1 - Data transmission system - Google Patents

Description

SCR / POCH for (HH; iXl), I, y, liTOpoil P.OD --- CHOR.CH

1mo, avl of the reverse channel to the nepBo.viy output of the receiver control unit, and its output through the after-connected connected demodulator (iodco), channel, iipco6); i3oisaiiHM code, receiving register and register 151 to the output of the output unit. The second output of the receiver's control unit is connected to the nerve inputs of the divider register, which often specifies the register of the specified checksum and the checksum register with a cyclic shift. The first outputs of the divider register and the cyclically shift checksum register are connected to the first input of the control unit of the terminal. The output of the unit is connected with the switching terminal and the receiver is connected to the second inputs of the divider register with a frequency setting.

Information accumulated on a perforated or magnetic tape is entered into the transmitter and transmitted by blocks of constant length through a telephone reception link where it is monitored for correctness of the information, recorded on the magnetic tape and issuing control signals through a return cable to the transmitter.

In the specified information transmission device, data is encoded in code 2 of 5 for increasing reliability, which allows for error, but limits the number of encoded and transmitted symbols and thus the device for transmitting information consisting of any characters and a variable number characters in service words. The principle of feedback in the transmission of information in a continuous stream is carried out using three storage devices in the transmitter, therefore the information is transmitted in blocks of fixed length and equal capacity of one storage device, and this, in turn, causes difficulties in compiling the initial transmission data. In the receiver of the device, information is recorded only on a fly by means of a tip on a magnetic tape, and random-access memory is used to match the speed at which information is received from the communication channel with the speed of recording on the magnetic tape, which also limits the use of the known device and stores it.

The purpose of the present invention is to improve the performance of an information transmission device and reduce equipment.

The goal is achieved by the fact that in the proposed Device, the transmitter contains a character length register, a status number register, a state decryptor, a state buffer register, a forward and inverse synphating n false code word generation unit, a reverse channel level indication unit and an arithmetic adder and the receiver is the phase mismatch register, the block of change of the division factor,: 1pI (|) iiKTKiiii summgpor, repair of the counter of length cHjMBu.ia, pcrninp number of numbers, state decoder, buffer register) state, approx said layer direct kaimla unit regeneratsip function words n deP1pf; a1or overhead c-ioii, syn (}) aziruk) H1, k (shbipaiy and 11os11mvol1) Iogo control. The first input of the arithmetic adder of the sensor is connected to the second outputs of the register

The divider is used to set the value, the 1-digit control value and the co-trollable sum with the cyclic shift and the first outputs of the counter registers of the character length and state number. The second input of the transmitter arithmetic adder is connected to the outputs of the receiving register and the control unit first. the inputs of the registers of the state number and the symbol length counter. The output of the arithmetic adder is connected to the corresponding input of the transmitter code conversion unit, its second inputs of registers of the symbol length counter, the symbol of the control amount, the cyclic shift checksum and the state number and the third input of the frequency divider register. The output of the reverse channel demodulator via the reverse channel level indication unit is connected to the first input of the state buffer register, the second input of which is connected to the outputs

the external switching unit and the control unit and the third input of the counter register are character lengths. The second output of the latter is connected to the third input of the control unit, the fourth input of which is through the state decoder

connected to the second output of the state number registrar, the third input of the state number register register is connected to the output of the transmitter status buffer register, the input of the direct and inverse synchronizing and spurious code combinations generating unit to the output of the transmitter control unit, and its output to the corresponding input transmitter output register. The first input of the receiver's arithmetic adder is connected to

the output of the block of change of the division factor, the first inputs of the phase mismatch registers, the symbol length counter and the state number, the second output of the receiver control block, the input of the regeneration block

words, the output of which is connected to the corresponding input of the output register, the second input of the phase mismatch register, the output of the receiving register and the first input of the decryptor of elastic words, synphasing combinations and

character control The output of this decoder is connected to the second input of the control unit, and the second input is connected to the output of the external switching unit, the first input of the buffer status register and the second input of the character length counter register. The second input of the arithmetic adder and receiver is connected to the outputs of the phase mismatch registers and the labeled checksum, the second output of the peiHCTpoB divider is often ibi nk (lpro, which is cyclically shifted, the first output of the registers of the symbol length counter and the number of the block and the input j of the offset and the number of the state and the input of the cyclical shift of the factor and the status number and the input of the shifting offset. The output of the receiver arithmetic adder is connected to the third inputs of the phase mismatch registers, the frequency divider, and the symbol length counter, the nerve input of the control unit, the second inputs are register An uncoupled checksum, a cyclically shifted checksum and state numbers and the corresponding input of the receiver code conversion unit. The corresponding output of the forward channel demodulator is connected to the second input of the status buffer, the first input of which is connected to the first output of the control unit, and the output to the third input of the state number register, the second output of which is connected to the second input of the receiver control unit through the state decoder. The output of the symbol length counter register is connected to the first input of the receiver, and the third output of the master frequency divider register is connected to the fourth input of the phase mismatch register.

The drawing shows the block diagram of the transmission device information.

The device contains a transmitter 1, a telephone connection 2 and a receiver 3.

The transmitter 1 includes an arithmetic adder 4, a register 5 divider of the master frequency, a register 6 of the symbol length counter, a register 7 of the designated checksum, a register 8 of the control sum with an initial shift, the register 9 of the state number, the reception register 10, block 11 and a converter of the code, unit 12 Vnea commutator, buffer register 13 states, unit 14 controls, unit 15 indicating the return channel level, reverse channel demodulator 16, decoder 17, unit 18 forming forward and inverse synphasing and false code combinations s, the register 19 output vvodgyuy unit 20, a modulator 21, a forward channel and a line terminating unit 22.

Receiver 3 includes an arithmetic adder 23, a phase mismatch register 24, a master frequency divider register 25, a symbol length register 26, a pozng register 27, a temp control register 28, a cyclic shift register 28, a state number 29, receiving register 30, dividing coefficient dividing unit 31, code converting unit 32, external switching unit 33, buffer state register 34, control unit 35, forward channel level indicating unit 36, 37 state decoder, service word deiterm 38, block 39 regener tion function words, output register 40, the demodulator 41 of the forward channel, line terminating unit 42, pin block 43 and the reverse channel modulator 44 Torr.

To the input of the arithmetic adder 4, the registers 5-10. The output of the adder 4 is connectors with the input of register 5, the switch fi, the register 7, the register 8, the register 9 and the block AND convert the code.

B, -: Approx. 2 external commits are connected to registers 5 and 6, the buffer peger of 13 states and the control unit 14.

A control block 14 and a kazai block 15 of the return channel connected to the demodulator 16 of the reverse kan, m are also connected to the input of the buffer register 13 of states. The output of the buffer status register 13 is connected to the input of the state number register 9.

To the input of the control unit 14 are connected: register 5, register 6, receiving register 1 and 10

register 9 via 17 states. The output of the control unit 14 of the pod, tichen to registers 5-10. to the arithmetic adder 4 and through the block 18 of the formation of direct and invstnoy synphating and false code

combinations to the output register 19, as well as to the input block 20.

A register of the 7-digit checksum, a register 8 of the checksum with cyclic

the shift and the input unit 20 through the receiving register 10. The output of the output register 19 through the AND conversion code, the modulator 21 of the direct channel and the linear matching unit 22 in conjunction with the telephone communication channel 2,

to which, via the linear matching b.yuk 22, the demodulator 16 of the reverse channel is connected.

NP HcpBbii arithmetic adder input 23 subkeys registers: 24 iesovpadadey

phases, 25 cases, 1 ate the frequency, 26 counters of the symbol length, 27 iosiachia coptros. sums, 28 MONITORED sums with a cyclic shift, 29 state numbers: and: 1 second input - irregular register 30 and block 31

changes in the division coefficient, the input of which is connected with the regime of 24 phase mismatches. The output of the adder 23 is connected to the inputs of the registers 24-29 and b, the current 32 of the conversion code,

To the input of the register 24 is connected to the register 25 divider of the master frequency and the receiving register 30.

The B.yuk of the external switching 33 is connected to the register 25 of the master frequency divider, the reggstow 26 counter of the symbol character and the buffer state of the 34 states, the control unit 35 is connected to the input of the latter, 1 and the block 36, indicating channel. The output of the buffer register is 34 states and sockets with the input of the register 29 state numbers.

To the input of the block 35, the control of the sub-outputs of the Registers 25. 26, 28, the arithmetic schemator 23, the decoders 37-39,

The input of the 37 stateful decoder, typed to the output of the register 29 of the state number. The input of the decoder 38 is connected to the output of the receiving register 30 and to block 33 comM Taiuin. The output of the control unit 35 is connected to the registers 24-29, the buffer register 34 of the states, the arithmetic adder 23 and through the unit 39 of the regeneration of the service spruce to the output register 40. The input of the continuous register 30 through the code conversion unit 32, the forward channel demodulator 41 to the linear matching unit 42 is connected to the telephone communication channel 2, and its output through the output register 40 to the output unit 43. The input of the linear matching unit 42 is connected to the unit 35 via the return channel modulator 44, and the output through the forward channel demodulator 41, with the forward channel level indication unit 36. The device works as follows. After starting up the equipment, the pulses from the setting generator (not shown in the drawing) of the transmitter control unit 14 of the transmitter 1 and the control block 35 of the receiver 3 arrive at registers 5 and 25 of the master frequency divider, respectively. The contents of these registers are transferred to arithmetic adders 4, 23, where one is added, fed back to the inputs of the registers and stored. The value of the accumulated number in registers 5, 25 is determined by the transmission speed and is set using external switching blocks 12 and 38, after which the divider registers of the master frequency 5 and 25 are extinguished and the division cycle is repeated. With each cycle of frequency dividing by the control units 14, 35, a sequence of clock pulses is generated for synchronization by the operation of the individual units of the device, and one is added to the contents of the registers 6 and 26 of the symbol length counter via arithmetic totalizers 4, 23. The register content is increased to a value equal to the transmitted code and specified using external switching blocks 12 and 33, after which registers 6 and 26 are extinguished and the accumulation is repeated. The operation of the device is controlled by the registers 9 and 29 of the state number through the control blocks 14 and 35. The operation algorithm of the device is divided into the following states: synphasing receiver 3; search for the service word "Start message; transfer of information and search for the service word "End of message; the transfer of control circuits; waiting for a decision on the transmitted block: message; reversing a transmitted or transmitted message block; detection by the transmitter; error detection by the receiver and the formation of the service command “Error; transcoding service code words. With the first frequency division cycle, the transmitter 14 / prvvlsii unit 1, through the arithmetic adder 4, writes one into the state number register 9. In the presence of the number 1 in the state number register, the control unit 14, with the help of the unit 18, forms a direct and inverse in-phase and spurious code combination and outputs an inverse in-phase combination on the output register 19. In accordance with the number recorded in register 6 of the symbol length counter in the transmitter 1., the corresponding digit of the register of the output 19 and transmissions to the code conversion unit 11 is read. Conversion of the parallel code to the serial one takes place. The sequential code elements read through the forward channel modulator 21 and the linear matching unit 22 are output to the telephone communication channel 2. At the same time, in the receiver 3, in accordance with the number taken up in the register of the character length counter 26, the code conversion unit 32 permits indifference to the corresponding bit of the receiving register 30. In the information transfer receiver, the transmitted elements of the serial code over the telephone channel 2 are connected through a linear the matching block 42, the forward channel demodulator 41, the code conversion block 32 and the receiving register 30 are fed to the phase mismatch register 24, where the mismatch of the edges of the incoming signals is recorded with the signal Lamy, coming from register 25 driving frequency divider. After the packspi of a certain number of inconsistencies with the register 24, a front advance or lag signal is output to the block 31 for changing the division factor. At the same time, with the next pulse from the master oscillator, the content of the register 25 of the master frequency divider is added to zero or two, respectively. During receiver syncing, the incoming code elements of the inverse synphasing compositions are accumulated by elements and shifted by an arithmetic adder 23 and a cyclic-shift checksum register 28. The decoding by the control unit 35 on the register 28 of the inverse sapphasing combination is indicative of the implementation of the identified synphasing, whereby the receiving register 30, the counter register 26 symbol lengths and the cyclic shift register 28 are extinguished. After re-decryption of the inverse synphating combination by the decoder 38 of service words, synphating combinations and character control, the control unit 35 is fed back through the modulator 44 of the reverse link and the line matching unit 42 issues the Start to transmitter 1 command and the arithmetic adder 23 adds one. Receiver 3 enters the waiting state of the service word "Start of message. The “Start via linear matching unit 22” incoming channel command

9

the transmitter 1, the reverse channel demodulator 16 and the reverse channel level indication unit 15 are supplied to the control unit 14, which adds the state number 4 through the arithmetic adder 4 to the content of the service word "Start of the message." In this state, the transmitter control unit 14, 1 issues a request for information to the input unit 20.

The decryption of the service words of the transmitted information is performed taking into account the codes and the number of characters specified by the external switching units 12 and 33.

When decoding in transmitter 1 by control unit 14 at receiving register 10, and at receiver 3 by decoder 38 at receiving register 30 of service words, the start of the message through the buffer registers 13, 34 of the state and registers 9, 29 of the number of information and search for service words "Error or End message.

After decrypting the service words, the start of the message, the code combinations from the iriem registers 10 and 30 are sent by control block 14, 35, respectively, where they are combined with the registers 7 and 27 of the designated checksums and the cyclic shift registers 8 and 28.

If an input error is detected in transmitter 1 or when the control unit 14 controls a tape break, transmitter 1 is transferred to the Stop state by writing the corresponding number to the state number 9 in the state status register 9, and from the output register 19 1 to the receiver 3, erroneous code combinations are issued.

Upon detection of the service word on the receiving register 10, the Error control unit 14 transfers the transmitter 1 to a state during which erroneous code combinations are output to output register 19 by the native and inverse synphous and false code combinations block 18, which act on the telephone link 2 to receiver 3 will be the reason for the appearance of the command “Reverse. But in this case, control block 14 will not execute this command. When the transmitter 1 detects the “Reverse incoming channel” command, in the case when there was no “Error” code, the transmitter 1 will repeat the transmitted information block.

If the "End of message" codeword is decrypted, a unit is added to the contents of register 9 of the state number and the transmitter 1 transitions to the next state in which it transmits the checksums.

If, in the code search state, the message starts at receiver 3 after the synphasing combination is decrypted by the decoder 38 of the service words, the synphating combination

ten

In the subsequent eight code combinations, the word "Start of message" does not appear, then the Reverse control unit 35 is sent via the reverse channel modulator 44 and the "Reverse" command is sent to the line matching unit 42, and the number register 29 is written initial state.

During the reception of information when signals from the direct channel level indication 36 or decoder 38 are received, the control unit 35 outputs to the register 40 the service code word "Error with the help of the office service regeneration unit 39. In this case, the initial state is recorded in the register 29, and a reverse command is sent to the transmitter 1 via the modulator 44, the linear matching unit 42 and the telephone communication channel 2.

After transferring to the service word "End of the message, the transmitter control unit 14 transmits to the output register 19 the contents of the checksum register 8 with a cyclic shift and the register 7 of the significant control

amounts.

After being deciphered by decipher 38 on the receiving register 30 of the code "The end of the message, the signal of block 35 is output to the arithmetic adder 23 the contents of register 28,

and from the receiving register 30 an inverse checksum is transmitted from transmitter 1. When the checksums coincide, the signal from the arithmetic accumulator 23 is sent to the control unit 35. The latter gives out

a signal to output a significant checksum from register 27 to the arithmetic adder 23, where the same is compared with the checksum received from the transmitter 1. If the checksums are not

match, then the service code word Error has been transferred to the output register 40 by the word word regeneration unit 39. In this case, the state number is written to the state number register 29, which corresponds incorrectly.

received message block, but in reverse

channel through modulator 44 reverse channel

and linear matching unit 42 is transmitted

team "Reverse.

If the checksums match, block

35, the control unit adds the state numbers to the register 29, after which the register 40 outputs the regeneration unit 39 and the service words "End of message" are output, and the "Start.

After transmitting the two checksums, the transmitter unit 14 of the transmitter 1 into the state number register 9 writes the number corresponding to the command waiting state from the reverse

channel and after sending the message block. In this case, block 14 outputs, via block 18, the direct in-phase combinations to register 19.

After a correctly received message and output of the message words of the end of the message on the receiving register 30 by means of a denithfrator 38

The generated inverse synphating combination is a sign that the transmitter 1 has failed to execute a command. In this case, block 35 records the number corresponding to the stop state of receiver 3 in register 29, and a reverse command is issued on the reverse channel. If, after a correctly received block of messages on the receiving register 30, the decoder 38 decrypts the direct in-phase combinations, this will indicate that the transmitter 1 has executed the commands sent on the reverse channel and the control unit 35 writes the number corresponding to the reception resolution to the register 29 the following message block that occurs in the manner described above.

In the case of deciphering by the transmitter 1 of the command "Reverse, the control unit 14 of the state register 9, state 9 records the number corresponding to the error in the transmitted message. At the same time, combinations with errors are written to the output register 19 by the direct and inverse sn and phasing and false code combinations 18, which through the code conversion unit 11, the forward channel modulator 21 and the linear matching unit 22 enter the telephone link 2 for transmission receiver 3 acknowledgment of an error in the information.

If the transmitter 1 is transmitting information from the computer, the control unit 14 on the register 9 records the number corresponding to the initial state of the transmitter 1, and a signal is sent to the computer. If the information is entered from a punched tape, the control unit 14 adds one to the contents of the state number register 9 and the transmitter 1 does not match the state corresponding to the reversal of one information block. When reversing a punched tape, the code combinations are read and receive the receive register 10, where the service words "Start of a message and an additional feature that is used to increase the reliability of the transmission and reduce the likelihood of loss when reversing a message block are deciphered. In order to reduce the likelihood of false repetitions of a message block, as well as the loss of these information blocks during reversals due to distortions of commands in the feedback channels, after each reversal, the sign of the reversal of the message block by transmitter 1 is transmitted to the telephone communication channel 2 combinations.

In the receiver 3, at the external switching unit 33, the corresponding transcoding characteristic of the service words is typed after each reception of the response word. The message start by the control unit 35 to the state number register 29 is set to the corresponding position at which for each block the transmission message Start posts and End message

are written in the external switching unit 33.

Using an arithmetic adder and common registers connected through appropriate external switched and controllable elements allows performing the same functions of shift registers, dividers, counters, etc. on the same set of elements during the transmission of one block of information. application for these purposes structurally separated and complex functional blocks.

The proposed information transmission device is distinguished by high reliability,

simplicity and versatility, consisting in the ability of the device to operate both with a variable number of characters in blocks and in non-responsive words, and with the standard number of bits in the characters and preserving

The changes in the maximum transmission speeds of up to 100 or 200 characters per second at a transmission rate per telephone channel of 600 or 1200 binary characters per second, respectively.

Форм} л а and 3 o b r e e and u

A transmission device of information, containing a non-distributor in which the output of the input

block through the serially connected receiving register, output register, block converted code and the modulator of the channel are connected to the input of the linear one of the unit, one output of which is connected to

| the output of the non-spacing sensor, and e) the output is connected to the input of the reverse channel demodulator, the first Bxoj of the control unit of the non-transmitting sensor is connected to the output of the receiving register, and its output is connected to the nerve inputs of the register

the master frequency divider, the register of the designated checksum, the cyclic shift checksum register, the input of the input unit and the corresponding input of the receiving register, the output of the current transmitter switching unit is connected to the second inputs of the control unit and the frequency divider register, the first output of which is connected to the third input of the unit Enumerations, outputs of registers of a designated checksum and a cyclic shift checksum are connected to the corresponding input of the transmitter's output register, output otorrhea through a telephone communication channel connected to the inlet nriemnika, wherein the first input line consent) aoschego unit connected to the receiver input, the second input - through modulation Torr reverse channel - to the first output of the control unit nriemnika and its output through series connected demodulator

the direct channel, the code conversion unit, the receiving register and the output register are connected with the input to the upper unit, the second output of the receiver control unit is connected to the first inputs of the master frequency register,

rspstra inactivity checksum and re13

The cyclic shift niCTpa checksum, the first outputs of the frequency divider register and the cyclic shift checksum register are connected to the first input of the receiver control unit, the output of the external switching unit of the receiver is connected to the second frequency register, which is designed to reduce equipment and performance improvement, in it the transmitter contains a register of the symbol length counter, a state number register, a state decoder, a buffer state register, b forming the ir and inverse synphating and spurious code combinations, the reverse channel level indicating unit and the arithmetic adder, and the receiver contains a phase mismatch register, a dividing ratio changing unit, an arithmetic adder, a symbol length counter register, a state number register, a state decryptor, buffer status register, block of direct channel level indication, block of regeneration of control words and descrambler of control words, fine phase combinations and character-by-character control, first input of arithmetic the transmitter adder is connected to the second outputs of the splitter registers of the master frequency, the coitro sum and the checksum with cyclic shift, and the first outputs of the registers of the symbol length counter and the state number, the second input of the transmitter arithmetic adder is connected to the outputs of the small register and the control unit and the first inputs the registers of the state number and the counter of the symbol lengths, the output of the arithmetic adder is connected to the corresponding OUTPUT input of the transmitter code conversion unit, with the second inputs p the symbol length counter, an individual checksum, a cyclic shift checksum and the state number and the third input of the frequency divider register, the output of the demodulator of the return drip is connected to the first input of the state buffer register, the second input of which connected to the outputs of the external switching unit and the control unit and the third input of the register of the symbol length counter, the second output of which is connected to the third input of the control unit, the fourth input of which through deschifrator iodklyuchen state to the second output state number, the third register

14

Koropiiro 1111 is connected to the output of the transmitter status buffer register, the input of the block of forming direct and inverse synphating and false code combinations is connected to the output of the equalizer block of the transmitter and its output is connected to the corresponding input of the register of the transmitter output, the nerve input of the arithmetic adder of the transmitter and the junction key of the transmitter and the inverter output of the Kostjupn division unit change unit, the first inputs of the phase mismatch registers, the symbol length counter and the state number, the second output of the receiver control unit, the input of the regeneration unit function words which is connected to Exit

the corresponding input of the output register, the second input of the register of non-coincidence of phases, the output of the pre-register register and the first input of the decoder of the service words, the sinting combination and the character control, the output

which is connected to the second input of the control unit, and the second input is connected to the output of the external switching unit, the first input of the buffer register 1 of the state and the second input of the register of the length meter S1vola, the second input

arithmetic receiver adder is connected to the outputs of regpstrov phase mismatch and positional checksum, the second output of the registers is the frequency divider and the control number with cyclic shift,

the first outputs of the counter registers the lengths of the symbol and the state number and the input of the block for changing the division factor, the output of the receiver's arithmetic adder is connected to the third inputs of the phase mismatch registers,

the divider of the reference and the symbol length counter, the first input of the control unit, the second inputs of the registers of the assigned checksum, the checksum with a public shift and the state number and the corresponding input of the receiver code conversion unit, the corresponding output of the forward channel demodulator through the direct level indication unit This channel is connected to the second input of the buffer register E1i, the first

the input of which is connected to the first output of the control unit, and the output is connected to the third input of the state number register, the second output of which is connected to the second input of the control unit via the state decoder

receiver, to the first input of which the second output of the register of the symbol length counter is connected, and the third output of the register of the master frequency divider is connected to the fourth input of the phase mismatch register.