SU1399795A1 - Message transceiver - Google Patents

Abstract

The invention relates to telecommunications and can be used to transmit and receive discrete messages. The invention allows to increase the speed of the device. On the transmitting side, the message from the output block 1 pulses from the clock pulse generator 2, post-acting to the inputs of the OF elements, 4, is rewritten into the register 5 and using the elements OR 6, 7 and the AND element 8 is read into the communication channel 10. At the receiving side, the received message using the And element and the clock generator is written to the register and fed to the output of the device. 4 il. (L

Description

co Stock I; D co wore

The invention relates to telecommunications and can be used in discrete information transmission systems.

The aim of the invention is to increase the speed of the device.

Fig, 1 shows a functional diagram of the transmitting side of the device; in fig. 2 is a functional diagram of the receiving side of the device; in fig. 3 and 4 are timing diagrams that explain the operation of the transmitting and receiving sides of the device.

Device for transmitting and receiving messages content on the transmitting side (fig, 1) input unit 1, generator 2 clock pulses, first, second elements OF, 4, shift register 5, first, second elements OR 6, 7, third element AND 8 and a zero potential bus 9, a communication channel 10, on the receiving side (FIG. 2) - an element 11, a shift register 12 and a pulse generator 13.

Device work; as follows

On the transmitting reset (Fig. 1) from the input unit 1 to the parallel inputs of the register 5 (code 3, a, -a) code combinations and to the second input of the And 4 signal are sent (a) the presence of the typed code combination of block 1, High level The signal (a) characterizes the presence of the dialed code combination, and the low level indicates its absence. The signal (a) of a high level at the inverse of the input element And 4 permits the passage of pulses (c) from the output of generator 3 to the control (e) input and inputs of the first and last bits of register 5. The first pulse that passed through the element 4 ( e) on the control input of register 5, writes to the register 5 signals (,., e) a parallel code combination acting on its inputs. In this case, the lower order (b) of register 5 is recorded 1, and the older (b-;) bit of register 5 registers the signals (b, -b -j) to register 5, the output (d) of the element OR 6 a high level signal is set, which passes through the I-UM 7 element to the second input of the AND 3 element, the inverse input of the AND 4 element to the input Reset of the input unit 1, the High level signal (s) resets the codog typed in block 1

50

five

0 0 5

0

five

combination, prohibits the passage of pulses (c) through the element 4 and allows the passage of pulses (c) from generator 2 to the clock input (e) of register 5.

Simultaneously, from the output (b) of the first bit of register 5, a high level signal is removed and a low level start signal is set, which is output to the communication channel 10. Under the action of clock pulses (e) in register 5, the binary information bits (b, –b) recorded in it are shifted. As the control input of register 5 has a zero potential, it is prohibited to write to it via parallel inputs, and when register is shifted into register 5, O due to the connection of the input of receiving serial information to the 9-potential bus 9. When entering the second bit (b) of register 5, the last 1, which was previously recorded in the last bit (b), the output potential (g) of the element OR 6 is set to zero, while if the output of the first discharge (b) is low (the signal level of the last binary information bit of the message is different from the level of the stop signal), then the output potential of the element And 8 is a high potential, which, having passed through the element OR 7, maintains a high level of the signal, if the output (b,) has a high potential (last dv signal level personal information bit of the message with the signal level Stop), then the output potential of the element And 8 is set to zero potential, which leads to the establishment of a zero potential at the output of the element OR 7, prohibits the passage of pulses (c) through the element And 3 and allows the passage of pulses (c) through the element 4. In the presence of the code combination in the input block 1, the cycle of the work of the transmitting side is repeated.

On the receiving side (FIG. 2) in the initial state in the last discharge of the shift register 12 is written 1, so that the second input of the element 11 is fed from the direct output of the last discharge (l) of the register 12 to high potential and to the input of the generator 13 clocks with last bit inverted output (m)

register 12 - zero potential. The input (b |) of receiving the sequential information of the register 12 and the first input of the element 11 of the communication channel 10 receives a high stop potential.

With the arrival of the Start signal at the first input (b) of the And 11 element, a zero potential is established, which causes the setting of a low potential at the output (s) of the And 11 element connected to the setup input of the register 12. Switching the signal (s) from high to low provides an entry in the register 12 of the code combination 100,., O, t, e, for the first digit (l) is written 1, and for the rest - O, the inverse output (m) of the last bit of the register 12 is set high potential, which includes a 13-clock pulse generator, and on the forward The last bit of the last register of register 12 sets a zero potential, which prohibits the passage of signals from the first input (b,) of the element 11 to its output (s) until the end of the reception of a code combination, From the output (k) of the generator 13, clock pulses ncfCTynaroT on the synchronization input of the register 12 shift. Since the input (b) of receiving the sequential information of the register 12 receives signals from the received code combination, and the clock pulses arrive at the clock input (k), the register

A shift is recorded when the code is received, combining the received signal. After writing to the register 12, binary information signals of the bits of the received code combination in the last digit (l) of the register is recorded 1, which at the beginning of the receive cycle the bit is recorded in the first digit (l) of register 12, Record 1

the last bit (l) of register 12 ensures the generator is turned off

13 and the readiness of the element 11 to select the Start signal at the beginning of a new cycle of receiving a code combination

The signals of binary information bits and the received code combination from the outputs (l, -l) of the bits of register 12 are output to the device. The appearance of a high potential at the forward output (l) of the last digit of the register 12 provides input of the received binary information bits of the message into the device interfaced with the receiving side,

With the arrival of a new starting signal at the input of the receiving side, the work cycle is repeated.

The technical advantages of the proposed technical solution in comparison with the prototype consist in increasing the speed of the device due to partial exclusion of the stop parcels from the transmitted message.

Claims (1)

Invention Formula A device for transmitting and receiving messages that contains an input unit on the transmitting side, whose information inputs are device inputs, the first outputs of the input block are connected to the corresponding first information inputs of the register, the first output of the register is connected to the communication channel, the clock pulse generator and the zero potential bus on the receiving side - a register and a clock pulse generator; the information input of the register is connected to a communication channel, characterized in that, in order to increase the speed of the device I, I elements and RSHI elements are entered into it on the transfer side, the output of the clock generator is connected to the first input of the first element I and the first direct input of the second element I, the output of the first element I is connected to the synchronizing input of the register, the second information input of which is connected To the zero potential bus, the second output of the register is connected to the forward input of the third element I, the first inverse input of which is connected to the first output of the register, the third outputs of the register are connected to the corresponding inputs of the first the OR element, the output of which is connected to the first input of the second element OR and the second inverse input of the third element AND, the output of the third element AND is connected to the second input of the second element OR, the output of which is connected to the second input of the first element AND, the inverse input of the second element AND and the input reset the input block, the second output of the input block is connected to the second direct input of the second element And, the output of which is connected to the controlling third and fourth information inputs of the register, on the receiving side entered element And The first input of which is connected to the St. channel. In, the element output AND is connected to the register setup input, the synchronization input and the register inverse output are connected respectively to the output and input of the clock generator, the direct register outputs are device outputs, the second input of the AND element is connected to the last of the direct register outputs. i, JTLJ Fiu.2 6, jTioimi ggpot VT {oo i / sh c m b to l one L-, H s P P . f