SU1381568A1 - Device for transmitting and receiving digital data - Google Patents

Abstract

The invention relates to communication technology, in particular, to the organization of information transmission between two intelligent terminals. The device allows to increase the reliability by synchronizing the process of receiving the information word into the transmitting part of the device from its receiving part, which eliminates the possibility of distortion of the information transmitted by the device. Receiving the information word to the transmitting part of the device (to register 1) is carried out in parallel code at its input 17 and control signal at input 16 when there is a request at output 18 generated at the output of trigger 3 when the input signal at its input element 4 of the comparison and upon receipt of the clock pulse from the output of receiver 6. In addition to the information word, the first and last bits of register 1 at input 16 record the beginning and end of the information word, and the penultimate bit is odd the output of the register 1, the level signal of the logical unit immediately after it is written to the first register register resets the request signal from the output of the trigger 3. The information word is transmitted from the output of the register 1 via the transmitter 5 in the serial code to the register 10 through the communication line 7 and the receiver 8 in sync pulses coming from the output of the chroniser 13 to the synchronization input of the register 10 and the synchronization input of the register 1 through the transmitter 9, the communication line 7 and the receiver 6. 1 Il. ( but

Description

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The invention relates to a communication technique and can be used for the exchange of information between computing and control complexes.

The purpose of the invention is the evolution of the reliability of information transfer.

The drawing shows skem device.

The device for transmitting and receiving digital information contains register 1, adder 2, trigger 3,:) comparison element 4, non-transmitter 5. receiver 6, communication line 7, receiver 8, transmitter 9. register 10, adder 11, Element I 12, Chronichitor IZ, Generator 14,:) The element I, 111-1Pl 15, Unranl Jupish input 16 devices, information inputs 17i 17 devices, ug1ravlyup1, iy output 18 devices, input 19 of the request, control output 20 devices , perp1,1e (outputs 21, - 21 registers and an exit 22 devices.

The device works as follows.

In the initial state, registers 1 and 10 are cleared, at the output of trigger 3 (device output 18) there is a request to the source subscriber for the transmission of an information word. In response to the request, the source subscriber issues an information word to register 1 at input 17, accompanied by a control signal, transmit it to input 16 at the control input of the register and to the first and last information bits of register 1.

fi is the last time) d register 1 from the output of the adder 2 receives the odd bit. At the moment that the information word is inserted into register 1, a signal of the LO1 unit level appears at its output, which resets the trigger 3 U to the initial state. At the same time, the logic unit level signal is fed through the non-transmitter 5, the communication line 7 and the receiver 8 to the input of the register 10 and is underloaded to its first bit along the falling edge of the sync pulse received from the output of the ILY-NE element 15. In addition, from the falling edge of the clock pulse, from the output of the element OR-NOT 15 through the transmitter 9, the communication line 7 and the receiver 6 to the synchronization input of the register 1, the information word in the register 1 is shifted by one bit. The process of transmitting the subsequent bits of the information word is repeated This way at 1stuning of the next sync pulses from the chroniser 13.

When a signal of the level of a logical unit arrives at the last digit of register 10, this signal is transmitted to the input element OR-NOT 15, prohibiting the passage of clock pulses to its input. At the same time, the same signal arrives at the output 22 of the device, notifying the receiving subscriber of the presence of an information word in register 10. / 6oHetiT-npHeMHnK reads information0

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the output word from the device output 21 and issues a request for the next information word by a logic unit level signal received through the device input 19 to the register 10 input. When information is reset from register 10, the logic zero level signal appears at its last output, which allows the sync pulses to pass through OR-NOT 15 element. At the falling edge of the clock from the output of receiver 6, the output of trigger 3 shows the request for the next information word that was present at its input from the output of element 4 alignment after the issuance of the register 10 of the last bit of the information word. Similarly, each information word is transmitted from the source subscriber to the destination subscriber.

In case of distortion of one or several bits of the transmitted information from the output of adder II, the receiver-receiver signal is sent through element I 12 to the subscriber-receiver.

Thus, the proposed device, in comparison with the known, allows to increase the reliability of information transmission due to the fact that in it the reception of the next information word from the transmitting subscriber is synchronized with the end of the reception of the previous information word by the receiving subscriber.

Claims (1)

Invention Formula A device for transmitting and receiving digital information containing on the transmitting side a register whose first inputs are the information inputs of the device, a comparison element whose output is connected to the first trigger input, a transmitter and a receiver, a transmitter output and a receiver input are connected to a communication line and on the receiving side, the receiver and the transmitter, the receiver input and the transmitter output are connected to a communication line, characterized in that, in order to increase the reliability of information transmission, it is inserted on the transmitting side an adder, the inputs of which are connected to the information inputs of the device, the output of the adder is connected to the second register input, the register outputs are connected to the inputs of the comparison element, the second trigger input and the transmitter input, the output of the trigger is the control output of the device, the receiver output is connected to the third trigger inputs and register, the fourth input of the register is the control input of the device, a register, a clock, an adder and an And element are entered on the receiving side, the output of the receiver is connected to the first input of the register, oh register input is input of device request from subscriber, first outputs 1381568 34 the registers are informational outputs AND and the input of the chronizer and are the outputs of the device and are connected to the inputs of the sum of the device, the output of the synchronizer of the subconnector, the output of which is connected to the third input of the register and The second output of the transducer, the output of the element I is the controller connected to the second input by the element output of the device.