SU1509913A1 - Device for interfacing user with computer - Google Patents

Abstract

The invention relates to computing and can be used to build computing systems based on multiplexed serial channels. The aim of the invention is to increase the reliability due to hardware control of information during transmission. The device contains an amplifier-receiver, an amplifier-transmitter, three switches, an encoder, a decoder, two registers, a shift register, a time counter, a pulse generator, a counter, a reference element, an OR element, an NAND element, three AND elements, three delay elements and two items are NOT. 1 il.

Description

The invention of onokit to computing and can be used to build computing systems based on multiplexed serial channels.

The purpose of the invention is to increase the reliability due to hardware control of information during transmission.

The drawing shows a block diagram of the device.

The device contains a receiver-amplifier 1, a decoder 2, a register 3, elements 4, 5, delay element 6, elements 7 and 8, delay element 9, counter 10, element 11 11, pulse generator 12, switches 13-15 , comparison element 16, shift register 17, registers 18 and 19, AND element 20, delay element 21, time counter 22, amplifier-transmitter 23, encoder 24, OR element 25, information input 26, control inputs 27-29, information output 30 and output 31 of the error sign.

Decoder 2 has an output of 32 characters. Command / data, serial data output 33, strobe output 34, word output 35 output, synchronization input 36 and information 37.

Encoder 24 has Commander / data attribute input 38, transmission start input 39, serial data input 40, synchronization input 41, reset input 42, word transmission output 43, data synchronization output 44, information output-45.

The amplifier-receiver 1 and the amplifier-transmitter 23 provide matching of the levels of the signals of the decoder 24, respectively, with the levels of the signals in the trunk lines. Decoder 2 determines match

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data output 33 to the used code, depending on the data, generates at the output 32 the sign of the Command / data, converts the code of the incoming Data into the output serial code at the output of the ЗЗ, accompanying each information bit of the code at the output 33 with the signal at the output 34, forms at the output 35 the sign of the presence reliable word output 37. Decoder 2 can be implemented using a chip K 588 VGZ.

Register 3 converts the serial data code from output 33 of decoder 2 into parallel code. Element HE 4 blocks signal propagation through AND 8 element if there is a sign. The command at output 32 of decoder 2. HE element 5 blocks the appearance of a signal at the input of the counter 10 at the time of receiving a word from the channel. The delay element 6 provides a delay in the propagation of the signal from the output 35 of the decoder 2 through the switch 14 to the input 39 of the encoder 24. With the aid of the element And. 7, a recording signal is generated in the TO counter. Using the And 8 element, a modification signal of counter 10 is generated. A delay element 9 provides a delay in propagation of the signal from the output 33 of decoder 2 through the switch .15 to the output 40 of the encoder 24. Counter 10 is used to determine the end of

dummy array of information. With the help of the element AND-NOT 11 the formation of the installation signal of the time counter 22 is carried out. The pulse generator 12 generates a sequence of signals that synchronize: the operation of the decoder 2 and the encoder 24. Switches 13-15 provide the transmission of signals to the inputs 38 - 40 of the encoder, respectively.

Using the comparison element 16, information is compared from the outputs of registers 3 and 18. Register 17 provides the conversion of the transmitted information from parallel to serial code. Register 18 stores the next word transmitted to the channel. A register of 19 stores the word; prepared for transmission to the channel. Moreover, the register 19 refers to the subscriber equipment. With the help of the element And 20, the error signal is generated due to the mismatch of the information transmitted to the channel and received from the channel. Element 21 Delay

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ki delays the arrival of the signal from the output 43 of the encoder 24 to one of the inputs of the And 20 element. The time counter 22 controls the length of the time interval during which the receipt of the next word of the array is not allowed, with the signal generator when it ends. Encoder 24 generates a sync pulse transmitted by the signal at input 38 (command or informational), converts the serial code of information 5 Madia at input 40 into an output code, transmits the specified word, generates an indication of the word transmission, as well as synchronization signals of the input information . Encoder 24 may be re-mapped using a K 588 VGZ chip. The OR element 25 serves to generate an error signal. The output 26 of the device receives the received data. Input 27 serves to transmit the trigger signal of the encoder 24. A signal at input 28 determines the mode of operation of the device. Input 29 serves to set the type of the transmitted word. From output 30, the transmitted data is sent to the trunk line. Device output 31 is used to transmit an error signal.

The device works as follows.

In the initial state, the counter 10, the registers 3, 17-19, the decoder 2 and the encoder .24 are in the zero state (not shown in the drawing for simplicity). At the same time at the output of the counter 10 there is a zero signal. As a result, a single signal is present at the output of the NANDI element 11, which keeps time counter 22 in the zero state.

The device operates in two modes: Exchange and Retransl chi. Mode selection is determined by the signal present at device 28. : In the Exchange mode, in accordance with the signal at input 28, device input 27 is connected via switch 14 to input 39 of encoder 24, device input 29 through switch 13 to input 38 of encoder 24, output register 17 through switch 15 to input 40 of encoder 24 In this mode, input 26 and device output 30 are connected to a single trunk.

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When receiving data from the device inputs 26, they are fed through amplifier-receiver 1 to the input 37 of the decoder 2. Decoder 2 checks the incoming data as belonging to the used code and if they are recognized as reliable at the output. 35, a decoder 2 appears a single signal. The output from the output 35 of the decoder 2 is fed to the input of the record of the register 3, the inputs of the elements And 8 and NOT 5. At the output of the element NOT 5, a zero signal appears, blocking the appearance of the signal at the output of the element And 7 and the element AND NOT 11. At the same time A single signal appears at output 32 of decoder 2 if the received word is an overhead (has a corresponding sync pulse), or a zero signal if the received word is informational. The output 33 of the decoder 22 is the sequential code of the received word, which is entered into register 3 on the leading edge of the signals at the output 34 of the decoder 2. After the last bit of the word arrives and the corresponding accompanying signal appears at the output 32 of the decoder 2, the output 35 decoder 2 is removed. Thus, at the outputs of register 3 there is a parallel code of the received word. If the received service word (there is a single signal at the output 32 of decoder 2), the reception of this word is completed (output 35 of the decoder 2 has a zero signal) 1: and the received service word is a command word (there is one in the corresponding received field ), a single signal appears at the output of AND 7. The signal from the output of the element 7, which enters the input of the record of the counter 10, records information determining the number of words in the received array and contained in the corresponding field of the control word. At the output of counter 10, a signal appears indicating that it is non-zero. Since at this moment in time at the input of the element -NE 5 there is a zero signal at the output of the element IS-NE 11, a zero signal appears enabling the operation of the time counter 22. The counter 22, according to the timestamp signals coming from the output of the pulse generator 12, counts the time interval until the next step appears.

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array. When the information word next to the command word arrives from the device inputs 26 and when it is recognized as valid, the signal at the output 32 of the decoder 2 is reset. As a result, at the output of the And 7 element, the write signal to the counter 10 is reset, and a single signal is formed at the output of the NOT A element. Simultaneously, a single signal appears at the output 33 of the decoder 2, and a signal appears at the output of the And 8 element, on the leading edge of which the counter 10 is modified. In addition, after the signal at the output 35 of the decoder 2 appears, the output of the HE 5 a zero signal is generated, at which a reset signal of the counter 22 is generated at the output of the NANDI element 11. Next, from the output 33 of the decoder 2, the serial code of the received word is fed to the input of the register 3, to which the signals from the output 34 of the decoder 22 are recorded.

If the received word is the last word in the received array, after modifying the counter 10, a zero signal is formed at its output, which enters the input of the AND-NOT element 11, the single signal from whose output keeps the counter 22 in the original zero system.

If the next received word is not the last one in the received array (a single signal is output at the output of counter 10), a zero signal is present at output 35, and the time interval during which no receipt of the next word of the received array is allowed is completed, at the output of counter 22 a single signal appears. When receiving information at the output 43 of the encoder 24, a zero signal is maintained, which through the delay element 21 and the AND element 20 arrives at the input of the OR element 25. As a result, a single signal from the output of the counter 22 through the OR 25 element enters the device output 31, indicating an error.

When transferring data from the device in the Exchange mode, the register 19 is pre-loaded with the data transmitted to the channel. A signal is sent to the input 29, which determines the type of the transmitted word (service, informational) and the input through the switch 13 to the input 38 of the encoder 24. Then to the input 27

The word start trigger signal is supplied through the switch 14 to the input 39 of the encoder 24. As a result, the output 45 of the encoder 24 generates a corresponding word start feature (sync signal) received through the amplifier-transmitter 23 to the output 30 of the device. Next, at the output 43 of the encoder 24 signal, on the leading edge of which the information from register 19 is recorded in registers 17 and 18. After the signal appears at output 43 of encoder 24 at output of element 21,

word from register 17 to the channel. Information about the output of the register 3 is fed to one of the inputs of the comparison element 16, the other input of which receives information from the output 18. Thus, at the inputs of the comparison element 16 there is information corresponding to the transmitted and received words. At the output of element 16, a comparison signal is generated. After resetting the signal at the output 35 of the decoder 2, a single signal appears at the output of the element HE 5 at the input

blocking the occurrence of an error signal at the output of the element I 20 until the word is transmitted, as well as receiving it from the channel.

a zero signal is supported, 15 elements are And 20. With the coincidence of data

at the inputs of the comparison element 16, a zero signal appears at the output of it; the input signal of the element is AND 20. As a result, no error signal is generated at the output of the element AND 20 From the output of the high bit of register 20. If 17 through the switch 15, the data on the data on the outputs of the element 16 is compared to the input 40 of the encoder 24. After the transition does not match, then a single signal is generated at the output of the element of the next bit at the output 44 of the channel 16 16 a signal is generated, which is transmitted through the input element 20, and the front of which is carried out by 25 ment OR 25 to the output 31 of the device,

signal error. The signal from the output of the AND element 20 is also fed to the input 42 of the encoder 24, resetting it to the initial zero state.

When transmitting information from the device with its reception from the channel in accordance with the described, in addition, the osuschig of information in the register 17.

Since the outputs 30 and the device inputs 26 are connected to a single line, simultaneously with the transmission of information, the inputs 26 enter the input 30 of the amplifier-receiver 1 and the input 37 of the decoder 2. If the received information is recognized as reliable, the output 35 of the decoder 2 generates a single signal arriving at the inputs of register 3, elements NOT 5 and And 8, element 6 delay. From the output of the element NOT 5, the zero signal arrives at the inputs of the element NAND 11 and the element AND 20, blocking the appearance of signals at their outputs.

At the output of the delay element 21, a single signal appears. It arrives at the input of the AND element 20: the time delay of the signal at the element 21, taking into account the possible time for the signal at the output 35 of the decoder after the signal at the output 43 of the encoder 24.

After the transmission of the last bit to the channel, the signal at the output 43 of the encoder 24 is reset, and a single enable signal is maintained at the output of the delay element 21. At this point in time at the output 35 of the decoder

2 there is a single signal (when the last bit is not finished), and the output of the element NOT 5 is zero. After the end of reception of information in the register

3 shows the recorded transmitted

There is a time control for the signal at the output. 35 of the decoder indicating the occurrence of the next word after receiving the previous word.

Further operation of the device during the transmission of information is carried out similarly to that described.

In the Relay mode, a signal is supplied to the device input 28, which connects output 32 of decoder 2 via switch 13 to output 38 of encoder 24, output 33 through delay element 9 and switch 15 to output 40 of encoder 24, output 35 through delay element 6 and switch 14 - to the input 39 of the encoder 24. The signal from the input 28 of the device in the Retransmission mode blocks the appearance of the signal at the output of the And 20 element.

In this mode, the inputs 26 and the outputs 30 of the device are connected to different trunk lines.

Claims (2)

Information from the device inputs 26 through the amplifier-receiver 1. is fed to the input 37 of the decoder 2. Assuming that the received information corresponds to the code used, the output 35 of the decoder 2 appears a signal indicating the arrival of data, and the output 32 of the decoder 2 a signal indicating the form of the received word (service, informational). The output from the output 32 of the decoder 2 goes through the switch 13 to the input 38 of the encoder 24. The signal from the output 35 of the decoder 2 enters the input of the delay element 6 and from its output through the switch 14 to the input 39 of the encoder 24, starts the encoder 24. The time interval the delay at element 6 is selected taking into account the delay in the appearance of the signal at the input 39 of the encoder 24 relative to the occurrence of the signal at the input 38 of the encoder 24. From the output 45 of the encoder 24, the generated sync pulse arrives at the input of the amplifier-transmitter 23 and further to the output 30 of the device . As two decoder bits appear at the output 33 of the decoder, they are transmitted through delay element 9 and switch 15 to input 40 of the encoder 24. The delay time of the signals on element 9 is selected taking into account the time interval required for generating the clock signal of this layer. When the signals are received at the input 40 of the encoder 24, the output 45 appears through the amplifier transmitter 23 at the output 30 of the device. In the process of transmitting an array of information in the Relay mode, control of the arrival time of the transmitted array is carried out as described. If the next word in the array is not received within a specified time interval due to a failure in the source of information or if interference occurs that leads to distortion of information at the device input 26, the output signal of the counter 22 generates an error signal through the OR element 25 at the device output 31. Claims A device for interfacing a subscriber with a computer, comprising an encoder, a decoder, two registers, a shift register, a first switch, wherein the information input of the shift register is connected to the information input of the first register and is the input of the device for connecting to the subscriber information input of the subscriber, and the output The data / decoder command is connected to the first the information input of the first commutator, the information output of which is connected to the Data / encoder input input, characterized in that, in order to increase the reliability due to hardware control of the information during transmission, a receiver-amplifier, amplifier-transmitter, two switches, a counter are inserted into the device , pulse generator, reference element, time counter, three delay elements, three AND elements, two NOT elements, AND element - NO, OR element, and the information input of the amplifier - receiver and information output of the amplifier The driver is the input and output of the device for connecting to the common computer bus, the output of the OR element is the output of ycTpofiCTBa for connecting to the subscriber error indication input, the second information input of the first switch and the first information input of the second switch are respectively the Command / data input and the start input the device, the first input of the first element I is connected to the first, second control inputs of the first, second, third switch. It is the switching input of the operation mode of the device, while the ion output of the amplifier receiver is connected to the information input of the decoder, the Data / command output of which is connected to the input of the first element NOT and to the first input of the second element AND, the output of which is connected to the recording input of the counter, the output of which is connected to the first input of the element AND –NE, output which is connected to the installation input of the time counter, the overflow overflow of which is connected to the first input of the SHS element, the second input of which is connected to the installation input of the encoder and to the output of the first And element, the second input of which is connected the second input of the NAND element, with the output of the second element NOT and the second input of the second element And, the third input of which is connected to the first information output of the second register, the second information output of which is connected to the information input of the counter, the counting input of which is connected to the output of the third element And , the first input of which is connected to the input of the record of the second register, with the output of the sign of the presence of the word decoder. II150 with the input of the second element NOT and with the input of the first delay element, the output of which is connected to the second information input of the second switch, the information output of which is connected to the transfer start input of the encoder, the information input of which is connected to the information output of the third switch, the first information input of which is connected to the output of the second the delay element, the input of which is connected to the information output of the decoder and with the information input of the second register, the synchronous input of which is connected to the gate output ohm of the decoder, the synchronous input of which is connected to the counting input of the time counter, with the output of the pulse generator and with P 312 the encoder synchronous input, the output of the word transmission feature of which is connected to the inputs of the recording of the shift register and the first register, with the input of the third delay element, the output of which is connected to the third input of the first And element, the fourth input of which is connected to the output of the comparison element, the first group of information inputs of which are connected to the first, second, third information outputs of the second register, the output of the first element is NOT connected to the second input of the third element AND, the second information input of the third switch is connected n with the information output of the shift register, the sync input of which is connected to the sync input of the encoder. thirty