SU1130854A1 - Information input device - Google Patents

Abstract

1. A DEVICE FOR ENTERING INFORMATION containing a selector, a data register whose outputs are an output information bus of a device, a first input of a data register is an input Device setting, the inputs of a data register group are an input information bus of a device, the first input of a selector is a sync input device, the first output is the gate output of the device, the inputs of the selector group are the device control bus, characterized in that, in order to improve speed by organization of synchronous operation, it contains a delay measurement unit and a synchronization unit, the first input of the delay measurement unit is connected to the first output of the selector, the second one, the input is a gate input of the device, and the group outputs are connected to the second group inputs of the synchronization unit, the first group inputs of which are combined with the inputs of the selector group, the second input is connected to the second output of the selector, the output by (L is connected to the second input of the data register and is the device request output, the first input of the sync-block ; The polarization is the clocking input of the device. : about Il X SP 4:

Description

2. The device according to claim 1, characterized in that the delay measurement unit comprises a generator, a trigger, a counter, a pulse driver, an element, the first input of which is connected to the output of the generator, the second input of the element AND is connected to the output of the trigger, and the output to the first the counter input, the second input of which through the pulse shaper is connected to the first trigger input, which is the first input of the block, the second trigger input, the second is the second input of the block, the outputs of the counter group are the outputs of the block group.

3. The device according to claim 1, stating that the synchronization unit contains a decoder, two delay elements, two 4I-IPI elements, a counter, a trigger, an NOT element, an AND element, the decoder group inputs the inputs of the second group of the block, the outputs of the decoder are connected to the inputs of the first group of the first and second element 4И-OR, the inputs of the second group of the second and second elements 4И-OR are connected to the outputs of the groups of the first and second delay elements, respectively, the input of the first delay element is first entrance

the block, the first trigger and the first counter input are the second block input, the counter output is connected to the second trigger input, the third trigger input is NOT connected to the output of the first 4I-OR element and the first input of the AND element, the second input of which is connected to the trigger output The output of the AND element is connected to the input of the second delay element, the output of the second element 4I-OR is connected to the second input of the counter and is the output of the block, the inputs of the counter group are the inputs of the first group of the block.

4. The apparatus of claim 1, wherein the selector comprises an address switch, a comparison unit, a register, a decoder, the outputs of the address switch are connected to the inputs of the first group of the comparison unit, the inputs of the second group of which and the inputs of the register group are the inputs of the selector group, the output of the comparison unit is connected to the first input of the register, the second input of which is the first input of the selector, the outputs are connected to the input of the decoder, the first output

which is the first output of the selector, the second output is the second output of the selector.

I

The invention relates to computing and can be used in the construction of control computing systems.

A device for exchanging information between a digital computer and external devices (WU) is known, containing a group of query buses, polls of a VU and a data input register, the output group of which is connected to a group of information inputs of a digital computer.

The device implements an asynchronous method of transmitting information from the sensor to the RAM of the digital computer tl.

The disadvantages of the device are low speed operations

exchange and throughput, the ability of the information highway, ensuring the connection of information sensors to a digital computer.

A device for exchanging digital computers with information sensors is known, which contains a selector, a data register whose outputs are an upper-floor device information bus, the first input of the data register is an input of the device, the inputs of the data register group are the input information bus of the device, the first input of the selector is the device’s sync input, the first output is strobe

3

The main output of the device, the inputs of the selector group, is the device control bus.

The device provides information transfer between the slave and digital computers via the direct memory access channel. As information from the sensor is available, it is written to the data register. At the same time, a signal is generated. A request arriving at the input of the computer. As soon as the direct access channel is ready, a request signal is received from the computer and a request is received, which reads information from the data register 21.

A disadvantage of this device is the low speed, due to the asynchronous operation of the sensor and the digital computer, in which the synchronization of information transfer between the sensor and the digital computer occurs during the transmission of each word of information. This leads to a large amount of time spent on the transfer of arrays of information from sources located over large distances. In addition, the device has a low data throughput capacity, which limits the number of information sources that can be connected to it.

I

The purpose of the invention is povyshenie

the speed of exchange operations through the organization of synchronous operation.

The goal is achieved by the fact that in a device for inputting information, containing a selector, a data register, the outputs of which are the output information bus of the device, the first input of the data register is input Setting the device, the inputs of the data register group are the input information bus of the device the selector input is the sync input of the device, the first output is the gate output of the device, and the inputs of the selector group are the control bus of the device, the measuring unit is entered delays and a synchronization unit, the first input of the measurement unit of the delay is connected to the first output of the selector, the second input is the gate input of the device, and the outputs of the group are connected to the inputs of the second group of the synchronization unit, the inputs

308544

the first group of which is combined with the inputs of the selector group, the second input is connected to the second output of the selector, the output is connected to the second 5 input of the data register and is the device request output, the first input of the synchronization block is the 1m input of the device.

The delay measurement block contains

10 generator, trigger, counter, pulse shaper, element And, the first input of which is connected to the output of the generator, the second input of the element And is connected to the output of the trigger,

f5 and the output to the first input of the counter, the second INPUT of which through the pulse shaper is connected to the first input of the trigger, which is the first input of the block, the second

20, the trigger input is the second block input, the counter group outputs are the block group outputs.

The synchronization block contains a decoder, two delay elements,

 two 4I-OR elements, a counter, a trigger, a NOT element, an AND element, the inputs of the decoder group are the inputs of the second group of the block, the outputs of the decoder are connected to the inputs of the first group of the first and second elements 4I-IPD, the inputs of the second group of the first and second elements 4I -OR connected to the outputs of the groups of the first and second delay elements, respectively, the input of the first delay element is the first input of the block, the first input of the trigger and the first input of the counter are the second input of the block, the output of the counter is connected to the second input of the trigger the third input of the trigger through the element is NOT connected to the output of the first 4I-OR element and the first input of the AND element, the second input of which is connected

45 to the trigger output, the output of the AND element is connected to the input of the second element .. the delay, the output of the second element 4И-Ш1И is connected to the second input of the counter and is the output of the block, the inputs of the counter group are the inputs of the first group of the block.

The selector contains an address switch, a compare block, a register, a decoder, and a switch output.

55 addresses are connected to the inputs of the first group of the comparison unit, the inputs of the second group of which and the inputs of the register group are the inputs of the selector group, the output of the comparison unit is connected to the first input of the register, the second input of which is the first input of the selector, the outputs are connected to the input of the decoder, the first output which is the first output of the selector, the second output is the second output of the selector. The introduction of these blocks allows to increase the speed of exchange by organizing a synchronous mode of information transfer from the slave to a digital computer. In this case, the request and information are synchronized with the clock grid of the digital computer, taking into account the propagation time of signals in the communication lines and the asynchronous operation of the digital computer and sensor 5, which allows reception of each word of the information array during one standard digital computer cycle. Fig. 1 shows the device diagram | FIG. 2 is a diagram of a delay measurement unit and a synchronization unit j in FIG. 3 is a diagram of the selector in FIG. 4 - time diagram of the device. The device (Fig. 1) contains a selector 1, a data register 2, a delay measurement unit 3, a synchronization unit 4, an output information bus 5, a control bus 6, a query bus 7, an information synchronization bus 8, a digital computer, a pulse bus 9, measuring signals tires 10 and 11, bus 12 for launching an array, bus 13 for installation, input information bus 14 for devices. Delay measurement unit 3 (FIG, (FIG. 2)) contains generator 15, trigger 16, counter 17, And element and pulse generator 19. Synchronization block 4 (FIG, 2) contains a decoder 20, two delay elements 21 and 22, two 4I-IPI 23 and 24, counter 25, trigger 26, NOT element 27 and element 28. The selector 1 (Fig. 3) contains the address switch 29, the block 30, the time register 31 and the decoder 32. The digital computer has a duty cycle the duration of Tn, consisting of eight so-called Comm. When the digital computer is in each cycle in cycles 7 and 6, the presence of a signal is interrogated by the Request on bus 7, and when it arrives at this moment, the digital computer clears the next cycle for the sensor code input operation address implements the channel GSPP DVR, Thus, all the request signals must be set at the time T6 tained on a computer input. In order to maximize the productivity of inputting an array of information, one working cycle is assigned to input each word. Signal duration The request is half the cycle of the digital computer, and to ensure reliable operation, the signal must be set at the input of the digital computer no later than T5 and removed no earlier than T7. Given these assumptions in FIG. 4 shows a temporary diagram of the operation of the device. The device works as follows. After connecting to the computer power system, the device hardware is reset, and the DVR is transferred to the initial start-up program, which produces measurement gates for each slave system in the form of corresponding control words (USL). The service is transmitted over the control bus 6 and is accompanied by a synchronization signal on the bus 8. In the selector 1, the number of the corresponding slave is determined by the address switch 29. When comparing the number of the VU encoded in USL with the number set on the address switch 29, the output of the comparison circuit 30 generates a signal that allows writing to the register 31 of a certain part of the bits of the ACL that are decoded by the decoder 32. The output of the decoder 32 is pin 10 through the pulse shaper 19, the counter 17 is reset in the delay measurement unit 3. At the same time, trigger 16 is set to one state by allowing pulses from the output of generator 15 to the counting input of counter 17, through element I 18. The frequency of operation of generator 15 is calculated based on the required accuracy of measuring the signal transit time on the bus line 10 and 11. In the particular case, the clock frequency of a digital computer can be used, which, with the corresponding timing diagram of a digital computer, can satisfy the necessary synchronization accuracy. The output signal of the decoder 32 simultaneously enters the bus 10, and the input of the digital computer and bus 11 returns back to the slave (transmitters and receivers installed at the ends of the communication lines are not shown). The return signal resets the flip-flop 16, and on the element 18 it is forbidden to receive counting pulses at the input of the counter 17. Thus, the code in the counter 17 corresponds to the time of signal propagation from the VU to the digital computer and vice versa. The counter code 17 is supplied to the input of the decoder 20, with the second bit of the counter 17 connected to the first input of the decoder 20, the third to the second input, etc. In this way, the time code is divided in half, i.e. at the input of the decoder 20, a code is actually set that corresponds (up to the least significant bit) to the signal delay on the line WU of the digital computer in one direction. The outputs of the decoder 20 are connected to the group of inputs of the 4I-IL 23 element. The second group of inputs of the 4I-IPI 23 elements are connected to the outputs of the delay element 21, at the input of which, since the power is turned on, the Gate CMV with a duration of TC / 2. The outputs of the decoder 20 and the delay element 21 are connected to the inputs of the 4I-OR 23 element in such a way that the output of the decoder 20 corresponding to the delay code fc connects the output of the delay element 21 with a delay equal to Tc - f3, i.e. delays the signal of the Strobe of the digital computer by an amount which is an addition to ti to the duration of the duration of the delay of the cycle cycle TC. Thus, at the output of the 4I-Sh1I 23 e-element, the Strobe of the CVM is synchronized and in-phase with the same signal in the CVM. I In this state, the device goes on until a signal is received to transfer an array of information, which is a signal driven by a CVM programming program, which is decoded by selector 1, and an Array Start signal appears on the output bus 12. This signal records into the counter 25 of that part of the DSP which determines the value of the transmitted array. The start triggering signal goes to one of the S-inputs of the trigger-; 26, to the second S-input of which the element is NOT 27. A signal is output from the element 4I-IPI 23. At this, the trigger 26 is set to one during the negative half-period of the output signal from the element 4I-IPI 23. The output of the trigger 26 through the element And, the signal to the input of the delay element 22 is allowed to pass. The delay element 22 and the element 4I-OR 24 carry out a delay of this signal by the value of TC - C3. The outputs of the decoder 20 and the delay element 22 are connected to the inputs of the 4I-OR 24 element in the same way as the 4I-OR 23 element. The output from the 4I-OR 23 element is read from the data register 2 and the information output bus 5 goes to the group inputs of digital computers. The same signal is fed to the input of the digital computer as a signal request. The latter and the information code, being delayed on the communication line, for a value arrive at the input of the digital computer at the time T4-T8 (Fig. 4), i.e. at the very moment when the digital computer analyzes the presence of an external query. Thus, in the next cycle, this information will be received in the DVR RAM. Upon completion of the array transfer, the output of the counter 25 generates a signal. End of the array, which flushes the trigger 26 into the zero junction: blocking the transmission of requests from the slave to the digital computer. In known devices, the time required for the transfer of an array of information is set to eT; T "" C No. - nep Acbfu. . where n is the number of words in the array; signal delay at the transmitter; signal delay at the receiver; delay of the signal in the communication line; the duration of the working cycle of the digital computer cycle; increment the duration of the working cycle of digital computers in exchange operations.

in the proposed device, the time required for jifia to transfer an array of information from n words is

(2)

 Fri.

+ t.

XjjcTp - c - shih

where is the synchronization time of the slave

and digital computers. Synchronization time t., ..- zat .1 / -I pn -

It is read only in preparation for the transmission of the array and is determined by the delay in the circuit: transmitter - communication lines - receiver and 1-2 operation cycles of the digital computer.

The delay in the circuit: the transmitter line of communication - the receiver in offer13085410

The device does not affect the transmission time of individual words in the array, since the transfer of the next word code information with the previous word's RAM into RAM is overlaid, since requests and information go on line, not waiting for the previous word reception confirmation signal. 10 Analysis of expressions (1) and (2) shows that the device in question shortens the transmission time of an array of information by an amount equal to

"Tr +

- t

np

m "s

.f + n

ds

 sync

Fig.Z

Claims (4)

1. INPUT DEVICE INFORMATION containing a selector, a data register whose outputs are the output information bus of the device, the first input of the data register is the input Device installation, the inputs of the group of the data register are the input information bus of the device, the first input of the selector is the clock input of the device, the first output is the gate output of the device, the inputs of the selector group are the device control bus, characterized in that, in order to improve performance by organizing synchronous mode The operation, it contains a delay measurement unit and a synchronization unit, the first input of the delay measurement unit is connected to the first output of the selector, the second, the input is the gate input of the device, and the outputs of the group are connected to the inputs of the second group of the synchronization unit, the inputs of the first group of which are combined with the inputs of the group selector, the second input is connected to the second output of the selector, the output is connected to the second input of the data register and is the output of the Request device, the first input of the sync * block is a clock input royals. and 2. The device according to π. 1, characterized in that the delay measurement unit comprises a generator, a trigger, a counter, a pulse shaper, an element And, the first input of which is connected to the output of the generator, the second input of the element And is connected to the output of the trigger, and the output to the first input of the counter, the second input of which the pulse shaper is connected to the first input of the trigger, which is the first input of the block, the second input of the trigger is the second input of the block, the outputs of the counter group are the outputs of the block group. 3. The device according to claim 1, characterized in that the synchronization unit contains a decoder, two delay elements, two 4-OR elements, a counter, a trigger, a NOT element, an AND element, the decoder group inputs are inputs the second group of the block, the outputs of the decoder are connected to the inputs of the first group of the first and second elements 4-OR, the inputs of the second group of the first ^; of the second and fourth 4-OR elements are connected to the outputs of the groups of the first and second delay elements, respectively, the input of the first delay element is the first input of the block, the first trigger input and the first counter input are the second block input, the counter output is connected to the second trigger input, the third input -trigger through the element is NOT connected to the output of the first 4I-IPI element and the first input of the And element, the second input of which is connected to the trigger output, the output of the And element is connected to the input of the second delay element, the output of the second 4I-I element And connected to the second input is the output of the counter and block counter inputs are inputs of the first group unit of the group. 4. The device according to p. ^ Characterized in that the selector contains an address switch, a comparison unit, a register, a decoder, the outputs of the address switch are connected to the inputs of the first group of the comparison unit, the inputs of the second group of which and the inputs of the register group are inputs of the selector group, the output of the comparison unit connected to the first input of the register, the second input of which is the first input of the selector, the outputs are connected to the input of the decoder, the first output of which is the first output of the selector, the second output is the second output of the selector.