SU1003064A1 - Information exchange device - Google Patents

Description

The invention relates to computing technology and automatic data transfer and can be used in information input systems in digital computers. A device for information exchange is known, which contains a meter control unit, a counter, a receive unit, a shift register, an overhead indicator, a linear buffer, a cell. making a request, the read control node performs data conversion during data exchange and does not have hardware for connecting to systems with redundancy 1. The closest in technical essence to the invention is a device comprising an input register, a command register and a control node, the first, second and third inputs of which are connected respectively to the clock source, the computer control device and the register register output, the inputs of the input register and the command register are connected respectively to the first output of the control unit and the computer memory, the second output of the control unit is connected to the computer control unit, and the output of the input register is connected to the memory E M. This device receives a serial code from an external device, converts it into a parallel one and outputs it to a computer storage device 23. A disadvantage of the known device is the inability to automatically connect or disconnect the information exchange device from an external device when using an exchange device in computer systems with multiple redundancy, when it is necessary to promptly switch an external device from a computer, i that is idle, to cut the first one The aim of the invention is to expand the functionality of the device by automatically connecting and disconnecting from the bus external device. The goal is achieved by the fact that the device for exchanging information contains a command register, an input register, a control unit, the first and second inputs of the control register unit, the control unit, the first and second inputs of the control unit being in the clock synchronous inputs device, the third inlet of the control unit is connected to the first output of the command register, the first input of which is the command input of the device, the first output of the control unit is signal in the device stroke, the second output the control unit is connected to the first input of the input register, the output of which is wired by the information output of the device; a receiving node, two elements AND, a pulse shaper, tr ger, and a third node are entered, the second output of the register command is connected to the first inputs of the receiving node and the first element I and the input of the pulse generator, the output of which is connected to the first zero input of the trigger, the second input of the input register and the fourth input of the control unit, the third output of which is connected to the second zero input of the trigger, the first input b control locator is connected to the second input of the first element I, the output of which is connected to the single trigger input and input of the delay node, the first and second inputs of the second element AND are connected respectively to the outputs of the delay node and the trigger, the output of the second element AND is connected to the second input of the command register and is the output of the device monitoring end signal, the third input, the input register is connected to the output of the receiving node, the second input of which is the information input of the device. Fig, 1 shows a block diagram of the device; in fig. 2 is a block diagram of the control unit. The device contains the receiving unit 1 block 2 control, the command register J, the input register 4, the first element AND 5, the pulse former, the delay node 7, the trigger 8, the second element 9, the inputs 10-13 of the device, 14-16 devices, generators 17 and 18 pulses, a group of 19 elements AND, elements AND 20-25, a counter 26, decoders 27 and 28, elements OR 29 and 30, triggers 31 and 32, The device operates as follows. From the computer memory, by the device command input 12, the command register is entered into the command register 3, which indicates the type of the external device, the method of packaging the information transmitted to the computer, the mode of operation of the system, including the exchange device and the computer, The first output of the control command register 3 to the control unit 2 generates the initial setting of the bits of the counter 26, which controls the reception of information in the input register 4. The initial code setting signals in the control unit 2 are fed to the first inputs of the corresponding elements AND group 19, the second inputs of which through the element OR 29 .. receives a strobe signal that accompanies the command. From the outputs of the AND elements of the group 19, the initial code is written to the counter 26. Thus, the number of bits of the information word accumulated in the input register 4 is established. The control unit 2. contains the first generator 17 of clock pulses, which ensures synchronization when transmitting information to the computer memory It is triggered by gating signals arriving at the sync input 11 of the device. The first generator 17 clock pulses forms two sequences of clock pulses ТИ1 and ТИ2. The second generator 18 of the clock pulses of the control unit 2 ensures the synchronization of the reception of information to the input register 4. It is triggered by clock signals arriving at the clock input 10 of the device. The second generator 18 clock pulses forms three sequences of clock pulses t, t, t. The operating mode signal from the second output of the register 3 of commands arrives at the input of the FO1 world of 6 pulses, while at its output certain pulses of a certain duration are formed to reset the trigger 8, the input register 4 and the trigger 31 of the control 2. Receiving node 1 contains a relay which is triggered when there is a signal at the second output of the register of 3 commands. Through the closed contacts of the relay of node 1 receiving information from an external device, input 13 of the device enters the third input of input register 4. The input register 4 is filled by control signals from the second output of control unit 2. The control signals in the control unit 2 are generated by the first decoder 27 connected to the outputs of the counter 26. The code unit on the counter 26 is incremented by the sync pulses of the sequence 12 through the AND 20 element. When the input register 4 is filled with information, the counter 26 of the control unit 2 overflows and the signal c the output of the second decoder 28, gated by the sync pulse of the t- sequence, through e: 1 and 25 sets trigger one 31 into one circuit. Then, using the sync pulse of the sequence ТI1, through el ment 24 and is set in a unit consisting of flip-flop 32. Since the output latch unit 32 to the signal output device 14 is provided presence information signal which enters, into the computer controller.

Then, in block 2 of control by the sync pulse of the sequence t, through the element 21 and the element OR 29, the initial code is set on the counter 26 through a group of 19 elements And connected to the command register 3.

By the sync pulse of the TI2 sequence of the AND 22 element, the OR element 30 is set to the zero state trigger 31, after which the sync pulse of the TI1 sequence is set to the zero state. the trigger 32. The control unit 2 is thus set to its original state.

Output register 4 consists of two registers (dynamic and static). The dynamic register accumulates information, which is then rewritten to a static register, from which it is written to the computer memory,

The copying of information from the dynamic register to the static one is carried out at the signal from the output of the AND 25 element.

In the presence of a signal at the second output of the register 3 commands, the pulses of the frequency from the output of the first element 5 come to the inputs of the delay 7 and the trigger 8, these pulses trigger 8 set to one.

From the third output of the control unit 2, the TI1 signals from the first generator of 17 clock pulses arrive at the zero input of the trigger 8, setting the trigger 8 to the zero state.

From the output of the delay unit 7 and the unit output of the trigger 8, the signals arrive at the input of the second element 9. The delay of the signal at node 7 is chosen so that at least one sync pulse at the third output of the control unit 2 will form a signal at its input and output.

In the event of a computer failure, the clock input 11 of control unit 2 no longer receives gating signals that trigger the first generator 17 of clock pulses, and therefore no signals are set to set trigger 8 to the zero state from the third output of control unit 2. Since the clock signals continue to arrive, the trigger 8, having set to one state by the signal from the output of the first element And 5, saves this state.

When a delayed clock signal appears at the output of the UE 7 delay from the output of the second element I 9, a signal is output to the device, which also sets the register of 3 commands to the initial state.

As a result of resetting the command register 3, the relay of the receiving unit 1 is turned off and by its contacts it disconnects the information buses of the external device from the input register 4, the passage of the clock frequency signals through the first element I5 is blocked. At the output of the pulse shaper 6, a reset pulse 8 is generated, the first trigger 31 of the control unit 2 is reset. The control termination signal from the output 16 of the device enters all computers of the computing system, and the highest priority computer is connected to the external device instead of the failed one.

Thus, the proposed device provides the ability to work in computing systems with automatic shutdown or connection to an external device — when the state of the computing system of the gel system changes. The use of the proposed device as part of a computer complex reduces information losses during exchange with external devices and improves the performance of the computer complex. Applications of the proposed device are especially effective in multi-channel information exchange systems that work with equipment in real time.

Claims (2)

1.Usoltsev L. G ,, Kislin B.P. Interconnection of discrete communication channels with a computer. M., Holy Hour, 1973, p. 102, fig. 3, 4. 2. Oychinnikrv V.I., Automatic information exchange device. M., Energie, 1971, p. 141, fig.511 I prototype). / J 70 // //