SU1012234A1 - Device for interfacing computer to communication channels - Google Patents

Description

trigger, two delay elements, six AND elements and four OR elements, with the first input of the first OR element connected to the fifth block input, the second input through the first delay element to the fourth block input and the first input of the second OR element, the second input of which is connected to the third input of the block, and the output to the zero inputs of the first and second flip-flops and the fifth output of the block, the first input of the first element I is connected to the second input of the block, the second input is connected to the third input of the block and the first input of the second element I connected by the second input to the first input of the block, the output of the clock generator is connected to the first inputs of the third and fourth elements AND of the synchronization node, the second input of which is connected to the output of the first OR element, and the output to the second output of the block, the single input of the first trigger, zero input of the third trigger and the first input of the third element OR, the output connected to the single input of the second trigger and the tenth output of the block, and the second input to the third output of the block and the output of the first element AND, the first and second inputs of which are connected to respectively with the output of the third flip-flop nuleBfcOM and. with the output of the first element And a single input of the third trigger, a single output connected to the first input of the sixth element And, the second input of which is connected to the third input of the block, and the output to the eighth output of the block and the first input of the fourth OR element, the output of which is the seventh output the second input is connected to the output of the second element I, the output of the second trigger is connected to the second input of the fourth element I, the output of which is the sixth output of the block, the output of the first trigger is connected to the ninth output of the block and the second input of the third element And, the output of which is connected to the fourth output of the block and through the second delay element to the first output of the block.

3. Device POP.1, characterized in that the code converter contains two pulse distributors, two registers, two groups of AND elements and an OR element, the group of inputs of the first register is connected to the group of inputs of the converter, the first inputs of the pulse distributors are connected to the fourth input of the converter and the first input of the second register, the group of outputs of which is connected to the first and third groups of outputs of the converter, the second inputs of the pulse distributors are connected respectively to the second and third inputs n eobrazovatel and group vyho. Dov - respectively, with the first inputs of elements And the first and second groups, the output group of the second pulse distributor connected to the fourth group of outputs of the converter, and the output - with the second output of the converter, the group of outputs of the first register connected to the second group of outputs of the converter and the second inputs of elements And the first group, whose outputs are connected to the group of inputs of the OR element, the output connected to the first input of the converter, the group of inputs of the second register is connected to the outputs of elements AND of the second group, the second inputs of which are connected to the second input of the converter.

.four. Device POP.1, characterized in that the comparison block contains a group of equivalence elements, a group of elements AND, an element AND and an element OR, the first and second inputs of the elements of equivalence of the group are connected respectively with the first and second groups of inputs of the block, and the outputs with the first inputs corresponding elements of the group, the second inputs of which are connected to the third group of inputs of the block, and the outputs - to the group of inputs of the element OR, connected to the output of the first INPUTCH4 of the AND element, the second input of the output which is respectively input output unit.

- one.

The invention relates to computing technology, namely to interface devices for controlling a computing machine (UVM) with communication channels, and can be used

when building control computing systems.

A known device for interfacing a computer with control objects, comprising reception / transmission registers, control registers, a counter, clock pulses, a block; Formation of control signals With the disadvantage of this device are the limited functionality due to the lack of control over the process of information exchange.  The closest to the proposed technical entity is a device for interfacing a computer with communication channels, containing a switch, the first input and output of which are the first input and output of the device, and the second input and output respectively are connected directly and through the control unit to the first output and the input of the code converter, the second input and the output of which are connected to the second input and output of the device through the buffer memory block, the first output of the control unit is connected to the address input switch ora, the second output through the pulse distributor with the address input of the buffer memory block, and the input group with the outputs of the elements of group I, the first inputs of which are connected to the output register group of the address register, and the second with the input group of the device and a group of inputs of the first element OR, the output of which is connected to the first inputs of the counter and the second element OR, the output connected to the first input of the trigger, and the second input to the third output of the device and the output. counter, the second input of which is connected to the third input of the device, and the third input to the fourth input of the device and the second input of the trigger, the output connected to the fourth output of the device, the input of the address register is the fifth input of the device 2 3The disadvantages of this device are limited functionality and low reliability of operation.  This device uses modulo control only for those messages that are issued in the UVM, and there is no possibility of resuming the information exchange operation, in the course of which there was a sat without recourse to the UVM program.  The control of the process of exchanging information on the time of exchange exchanged in this device is unreliable, not strong enough, and in the case of a fault, the device initiates the repeated exchange of information through. recourse to the UBM program, which leads to complication of the programs, inefficient use of computer time and reduced speed of information exchange and the entire control complex as a whole.  The purpose of the invention is the expansion of functional capabilities by analyzing the state of exchange and automatically resuming exchange operations in case of failures.  The goal is achieved in that the device containing the control unit, the code converter, the address register, the switch, the time counter, the OR element and the trigger, and the device start input is connected to the single trigger input, the output of which is connected to the device state output. time connected with  the first input of the OR element, the group of address inputs of the device is connected to the input register group of the address register, the first output and input of the converter are connected respectively to the first input of the switch and the output of the control unit, the second fourth outputs of which are connected respectively to the second - fourth inputs of the switch, the first output of the converter codes connected to the first input of the switch, the first - the fourth group of outputs of which are connected respectively to the first group of information inputs and the first, second to third groups of synchronization outputs of the device, and the first and second groups of inputs, respectively, with the first information and synchronization groups of device inputs, a comparison block, a fault counter and a register of features of operations are entered, the output address register group is connected to the switch control input group, the first and second outputs which are connected respectively to the second and third inputs of the code converter, the fifth and sixth outputs of the control unit are connected respectively to the first and second inputs of the counter, first, fourth, group of outputs of the code converter are connected respectively to the second information group of device outputs and to the first to third groups of inputs of the comparison unit whose output is connected to the second input of the OR element, the group of inputs of the code converter is connected to the second information group of device inputs, group of inputs . the register of features of operations is connected to the group of command inputs of the device, and the first and second outputs, respectively, with the first and second inputs of the control unit, the third, fourth inputs of which are connected respectively to the second output of the code converter and the first output of the fault counter, the output of the OR element is connected to the input of the fault counter, the second output of which is connected to the device failure output, the seventh and eighth outputs of the control unit are connected respectively to the zero input of the trigger and to the device request output And a fifth input - to the input of trigger device ninth and tenth control unit outputs are connected respectively to the input unit CPA Neny and fourth input body transform codes.  The control unit contains a clock pulse generator, a synchronization node, three flip-flops, two delay elements, six AND elements and four OR elements, the first input of the first element OR is connected to the fifth input of the block, the second input through the first delay element from the fourth: input the block and the first input of the second element OR, the second input of which is connected to the third input of the block, and the output to the zero inputs of the first and second flip-flops and the fifth output of the block, the first input of the first element I connected to the second input of the block, the second input from the third m input of the block and the first input of the second element And connected by the second input to the first input of the block, the output of the clock generator is connected to the first inputs of the third and fourth elements of AND and the synchronization node, the second input of which is connected to the output of the first element OR, and the output to the second output of the block, the single input of the first trigger, the zero input of the third trigger, and the first input of the third OR element, the output of the connected. with the single input of the second trigger and the tenth output of the block, and the second input with the third output of the block and the output of the fifth element And, the first and second inputs of which are connected respectively with the zero output of the third trigger and with the output of the first element And and the single input of the third trigger, unit output of the sixth element I connected to the first input, the second input of which is connected to the third input of the unit, and the output to the eighth output of the unit and the first input of the fourth OR element, the output of which is the seventh output of the unit, and A swarm input is connected to the second element And, the output of the second trigger is connected to. the second input of the fourth element I, whose output is the sixth output of the block, the output of the first trigger is connected to the ninth output of the block and to the second input of the third element And, the output of which is connected to the fourth output of the block and through the second delay element to the first output of the block.  The code converter contains two pulse distributors, two registers, two groups of AND elements and an OR element, the input register group of the first register is connected to the converter input group, the first inputs of the pulse distributors are connected to the fourth converter input and the first input of the second register,. the output group of which is connected to the first and third output groups of the converter, the second inputs of the pulse distributors are connected respectively to the second and third inputs of the converter, and the output groups - respectively to the first inputs of elements of the first and second groups, the output group of the second pulse distributor Connected to the fourth group of outputs the converter, and the output with the second output of the converter, the group of outputs of the first register is connected to the second group of outputs of the converter and the second inputs of the In the first group, the outputs that are connected to the input group of the element OR, the output connected to the first input of the converter, the group of inputs of the second register is connected to the outputs of the elements AND of the second group, the second inputs of which are connected to the second input of the converter.  The comparison block contains a group of elements of equivalence, a group of elements AND, an element AND and an element OR, the first and second inputs of the elements of equivalence of the group are connected respectively to the first and second groups of inputs of the block, and the outputs to the first inputs of the corresponding elements AND of the group whose second inputs are connected to the third group. the inputs of the block, and the outputs to the group of inputs of the OR element connected to the first input of the AND element, the second input and output of which are the input and output of the block, respectively.  The pulse distributors are, for example, a serially connected counter and a decoder.  The presence in the converter of codes of two independent registers and pulse distributors allows one-time transmission of the code to the communication channel and reception of the code from the communication channel in order to control the process of information exchange.  In addition, the construction of a parallel-to-serial code converter using a static register, a pulse distributor, a group of AND schemes and an OR scheme allows the conversion of codes without destroying the original information, unlike, for example, converters built on shift registers.  This makes it possible to organize in the device a hardware repetition of the operation without referring to the UVM program.  The comparator allows to perform bitwise comparison of the transmitted and received codes from the communication channel and form them. signal failure in case of a negative result compared to.  FIG. 1 shows a block diagram of the device; FIG. 2 is a functional block diagram of the control unit, per fig. 3 — Functional diagrams of the code converter and the comparison unit.  .  The device (figl) contains a control unit 1, a kodo converter 2.  unit 3 comparison, register 4 addresses, switch 5, register b signs of operations, time counter 7, the element OR 8, counter 9. faults, trigger 10, device inputs 11, device outputs 12-14, input 15-19 first, even. the first, second, and third groups of entrances; the outputs are 20–24 of the first, first, second, third, and fourth groups of exits. .  Control Panel 1 (FIG. 2) contains a generator of 25 clock pulses, triggers 26-28, delay elements 29 and 30, elements OR 31-34, AND elements 35-40 and synchronization node 41.  Converter 2 codes (FIG. H) contains valves 42 and 43. pulses, registers 44 and 45, elements of AND 46 and 47 of the first and second groups and the element OR 48, and block 3 of the comparison element and 49, the element OR 50, the elements of AND 51 groups and the equivalence elements of the 52 group.   Pulse distributor 42 has a bit width equal to M, and valve 43 has M + 2 bits, with M + 1 bits being represented as a group of outputs of distributor 43.  From this group M, the first bits are connected to the first inputs of the elements And 47, the bits from the second to (M + 1) -th are connected: - they are not connected to the fourth group of outputs of converter 2 and to the Second inputs of the elements And 51, the number of which in the group is equal to M.  In the mode of inputting information into the control object over the communication channel of the devices, the operation follows.  In the initial state from the output, three Gera 10, through output 12, the signal is received in the ACU. The communication channel is free.  At this signal, the UBM starts the information exchange operation.  Before the start of the signal exchange operation from the CCU, all the device memory elements are reset. .  At the inputs 15, 16 and 17 into register 4, register 44 of converter 2 and into register 6 of the ACU, corresponding codes are recorded.  The address code from the groups of outputs of the register 4 is fed to the switch 5, while the inputs 18.  and -19 and outputs 21-24 are connected to a select.  communication channel.  From the output of register 6 to the input of block 1, a signal is received to enter information into the communication channel.  From input 11, a single trigger input 10 and the fifth input of unit 1 from USh receive a Start signal, which starts the procedure for entering information into the communication channel.  In this case, the trigger 10 is set to a single state and with it.  output and output 12 before the end of the communication operation is removed, the signal is a communication channel. -free  From the fifth input of block 1, the signal is triggered through OR 31 to the input of node 41, on the first exit of which clock pulses come from generator 25.  At the same time, at the output of node 41 there is a transmission start signal synchronized with the clock grid of the device, which through switch 5 and output 22 is transmitted to the communication channel.  According to the same signal, the trigger 26 is set to one state and from its single output the resolving potential is fed to the input of the element I.  37, from the output of which the clock pulses are fed to the output of the control unit 1 i and to the input of the delay element 30.  From the fourth output of block 1, the clock pulses are shifted through the switch 5 and the output 24 to the communication channel.  1C, the first output of the block 1, the pulses delayed relative to the sync pulse shift come to the input of the distributor 42.  The signals from the group of outputs of the distributor 42 on the elements And 36 sequentially gate the signals from the outputs of the register 44, and from the output of the element OR 48 the serial code through the switch 5 and the output 21 is transmitted to the communication channel.  In this case, each code pulse at the output 21 is preceded by a shift pulse at the output 24.  To control the reception of information by the control object, a serial code is transmitted from it through the communication channel to the device, the code code being transmitted.  and the shift pulses, arriving respectively at the inputs 18 and 19, are delayed relative to the transmitted-code and shift pulses and can be unsynchronized with the tact device;  The serial code received from the communication link through the switch 5 is sent to. the second inputs of the elements And 47, and the shift clock pulses - to the second input of the distributor 4-3.  The signals from the outputs of the distributor 43 are fed to the input elements And 47 and allow the passage of code pulses sequentially at the input of the register 45.  In this case, from the outputs of register 45 to the first and third groups of outputs of converter 2, a parallel, code is transmitted, and after receiving the last shift clock pulse from communication channel c.  the output of the distributor 43 on WTO. The swarm output of converter 2 transmits an overflow signal.  From the third input of block 1, the overflow signal of the distributor 43 is fed to the input of the element and 36, to the other input through the first input of block 1 from the register b, the enabling signal of the input operation of information into the communication channel is received.  Further, the overflow signal of the distributor 43 from the output of the AND 36 element is transmitted to the input of the OR element 34, at the output of which a release signal of the communication channel is formed.  This signal, coming from the output of block 1, trigger 10, is set to the zero state, and from its output through output 12 of the device in the ACU, the signal is received again. The communication channel is free, indicating that the information exchange operation has completed.  The device performs the information exchange process in time.  On the signal the start of the transmission, the trigger 27 is set to the single state, and the signal from its single output permits the passage through the AND 38 of the sync pulses to the second input of the time counter 7.  Upon completion of the information input operation into the communication channel, the signal is overflowed by the distributor 43 from the second output of the converter 2 through the third input of unit 1 to the second input of the OR element 32.  By this signal, the unit 1 sets the reference state 7 to the initial state, and the triggers 26 and 27 are set to the zero state.  In this case, the output of the shift clock pulses to the switch 5 and the output of the clock clock pulses in the counter 7 time stops.  In the event that, over a specified time, the overflow signal of the distributor 43 is not received, a signal is generated that the counter 7 overflows, which is through the OR element 8.  enters the input of the account Chika 9 failures.  From the first output of the counter 9, a single failure signal is fed to the input of the delay element 29 and to the first input of the OR element 32.  In this case, the counter 7 and the triggers 26 and 27 are reset.  The delayed signal is a single fault from the output of the delay element 29 through the element OR 31 is fed to the second input of the node 41.  According to it, the start of transmission signal is formed, the distributors 42 and 43 and the register 45 are set to the initial state, and then the information is entered into the communication channel in the same way as by the Start signal received from the WLM. In this case, the information for the exchange is stored in the first register 44 of the previous exchange cycle in which the failure occurred.  Thus, the device resumes operation.  information exchange over the communication channel in the case of a single failure without recourse to the UVM program.  In the device, in the mode of entering information into the communication channel, continuous bitwise control of the transmitted and received codes is carried out.  To do this, in block 3 on the elements of equivalence 52, the codes recorded in registers 44 and 45 are compared bit by bit. .  Comparison of the results of comparison is performed by sequential gating on the elements 51 of the comparison results in each code bit by signals from the outputs of the distributor 43, and the result of the comparison of each bit is polled by a signal from the output of the next bit of the distributor 43.  This is necessary so that the comparison of each code bit can be made only after the end of the discharge of this bit from a parallel code to a serial one and from a serial one to a parallel one.  From the unit arm of the trigger 26, a signal is received at the input of the AND element 49 permitting the passing of the signal of bit comparison.  In the case of a negative result of a comparison, in any code bit the signal is a bitwise comparison from the output of block 3 through the element OR 8 is fed to the input of counter 9 and causes a repetition of the operation of entering information into the communication channel in the same way as in the case of time failure exchange.   In the mode of outputting information from the communication channel, the device operates as follows.  The transmission over the communication channel of a command to output information from the control object is carried out in the same way as in the information input mode.  In this case, a random control of the command transmission and control over the time of the exchange is carried out.  Upon completion of the transmission of the command to the communication channel, as in the information input mode, the trigger 26 and 27 are set to the zero state by the overflow signal of the distributor 43, block 1 generates a reset signal of the time counter 7 and stops issuing the sync pulses to the counter 7 .  However, from the output of the register b, the signal of the corresponding feature of the operation goes not to the first but to the second input of the control unit 1.  This leads to the fact that after the transfer of the command to the communication channel and its bit control by the overflow signal of the distributor 43, the channel release signal is not generated on the AND 36 and OR 34 elements, and the Ready to receive signal is generated at the output of the AND 39 element, which Through the third output of block 1, the switch 5 and the output 23 are transmitted to the communication channel, while from the tenth output of block 1 to the converter 2 transmits the reset signal to the initial state of the valves 42 and 43 and the register 45, and the trigger 27 is set to single state and with the sixth output of block 1 to the counter 7, the sync pulses begin to arrive again.  On the trailing edge of the overflow of the distributor 43, the trigger 28 is set to one state. In this case, the next overflow signal to the output of the AND 39 element is prohibited and it is allowed to pass to the output of the AND 40 element.  The signal Ready to receive the control object via the communication channel into the device at input 18 a word of information in a sequential code, accompanied by its shift clock pulses transmitted to input 19.  Conversion of received serial code to pa. Parallel is performed in the same way as when monitoring the input of information into the communication channel.  According to the overflow signal of the distributor - 4.3, entered in block 1, at the output of the element 40, a signal is generated. The request is transmitted to the ACU at output 14.  On this signal, a parallel code from the outputs of register 45 through the outputs 20 transmits from - to the ACU.  Simultaneously with the signal, the Request at the output of the OR element 34 generates a signal to release the channel, which sets the trigger 10 to its initial state, and from its output through output 12 to the ACU transmits a signal. The communication channel is free.  Upon completion of outputting the word of information from the communication channel, the distributor 43 triggers 27 to the zero state and stops producing the clock synchro pulses to the counter 7.  If, when outputting information from the communication channel, after a specified time after the Ready to Receive signal, the overflow signal of the distributor 43 is not generated by the overflow signal of the counter 7, virabatyv, the failure signal, by which the output of information from the communication channel is resumed, from issuing a command to the communication channel.  At the stage of receiving the requested information from the communication channel, the trigger 26 is set to the zero state, the output of block 1 does not have a bitwise resolution and this comparison is not made, since c.  In this case, the code received from the communication channel cannot be matched with another code.  When the code compares the transmitted and received codes from the channel, it can be detected.  If there is such a damage to the communication channel, device or control object, in which a random comparison signal cannot be generated, for example, when there is no reception of the shift sync pulses, the failure signal is still generated.  overflow time counter.  In the event of a repeated failure in the process of executing the same information exchange operation, regardless of the type of failure, the failure signal is removed not from the first, but from the second output of the fault counter 9 and through output 13 is transmitted to the ACU.  On this signal, the ACU connects the diagnostic test program to localize the fault location.  Thus, the proposed device has broader functionality than the prototype, since it provides for the bit-wise control of codes entered into the communication channel and performs a repetition of the operation, during which a single failure occurred, without prompting to the pro. gram uvm.  Expanding the functionality of the device entails an increase in reliability and an increase in the speed of the communication channel.  Improving the reliability of the communication channel is achieved due to the fact that the joint use of bitwise control. and the time control allows detecting virtually any faults and distortions in the transmission of information over the communication channel.  An increase in speed is achieved due to the fact that the resumption of the information exchange operation begins immediately after the detection of a fault during bitwise comparison, and not only after the passage of the control time.  In addition, at the expense of hardware repetition of the operation without rotation to nporpaNwe, UVM saves the computer time and memory of the UVM.

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Claims (3)

A device for interfacing a computing machine with communication channels, comprising a control unit, a code converter, an address register, a switch, a time counter, an OR element, and a trigger, the device trigger input being connected to a single trigger input, the output of which is connected to the device status output, the time counter output connected to the first input of the OR element, the group of address inputs of the device is connected to the group of inputs of the address register, the first output and input of the code converter are connected respectively to the first input of the switch torus and the output of the control unit, the second - fourth outputs of which are connected respectively to the second fourth inputs of the switch, the first one, the output of the code converter is connected to the first input of the switch, the first - fourth groups of outputs of which are connected respectively to the first group of information inputs and the first, second and third groups of synchronizing outputs of the device, and the first and second groups of inputs, respectively, with the first information and synchronizing groups of inputs of the device, characterized in that, for the purpose of Expansion of the functional capabilities of the device by analyzing the flow of data 'and the resumption of the automatic exchange operations in case of failure detection. a comparison unit, a failure counter, and a register of operation signs are entered into it, and the group of outputs of the address register is connected to the group of control inputs of the switch, the first and second outputs of which are connected respectively to the second and third inputs of the code converter, the fifth and sixth outputs of the control unit are connected with the first and second control inputs, the third, fourth of which are connected respectively by the second output are converted respectively with the first and second inputs of the time counter, the first fourth of the group of outputs of the converter I codes are connected respectively with the second information group of the device outputs and with the first third groups of inputs of the comparison unit, the output of which is connected to the second input of the OR element, the group of inputs of the code converter is connected to the second information group of the device inputs, the group of entries of the operation attribute register is connected to the group of command device inputs, and the first and second outputs, respectively, of the input block of the code codes and the first output of the failure counter, the output of the OR element is connected to the input of the failure counter, second whose output is connected to the device malfunction output, the seventh and eighth outputs' of the control unit are connected respectively to the zero input of the trigger and to the output of the device request, and the fifth input with the device start input, the ninth and tenth outputs of the control unit are connected respectively to the input of the comparison unit and the fourth input about t and 5B | s u GO ·, code converter. 2 · The device according to claim 1, wherein the control unit * comprises a clock pulse generator, a synchronization unit, three. a trigger, two delay elements, six AND elements, and four OR elements, the first input of the first OR element connected to the fifth input of the block, the second input through the first delay element with the fourth input of the block and the first input of the second OR element, the second input of which is connected to the third input of the block, and the output to the zero inputs of the first and second triggers and the fifth output of the block, the first input of the first element And is connected to the second input of the block, the second input is to the third input of the block and the first input of the second element And connected to the second input the first input of the block, the output of the clock generator is connected to the first inputs of the third and fourth AND elements and the synchronization node, the second input of which is connected to the output of the first OR element, and the output to the second output of the block, the single input of the first trigger, the zero input of the third trigger and the first input of the third OR element, the output connected to the unit input of the second trigger and the tenth output of the block, and the second input - with the third output of the block and the output of the fifth element And, the first and second inputs of which are connected respectively only with the zero output of the third trigger and with the output of the first AND element and the single input of the third trigger, the unit output connected to the first input of the sixth AND element, the second input of which is connected to the third input of the block, and the output with the eighth output of the block and the first input of the fourth OR element the output of which is the seventh output of the block, and the second input is connected to the output of the second element And, the output of the second trigger is connected to the second input of the fourth element And, the output of which is the sixth output of the block, the output of the first ggera connected to the ninth output unit and to the second input of the third AND gate, whose output is connected to the fourth output of the unit and through the second delay element to the first output unit. 3. The device according to claim 1, characterized in that the code converter contains two pulse distributors, two registers, two groups of AND elements and an OR element, wherein the group of inputs of the first register is connected to the group of inputs of the converter, the first inputs of the pulse distributors are connected to the fourth input of the converter and the first input of the second register, the group of outputs of which is connected to the first and third 'groups of outputs of the converter, the second inputs of the pulse distributors are connected respectively to the second and third inputs of the index, and the output groups, respectively, with the first inputs of the elements And the first and second groups, the group of outputs of the second pulse distributor is connected to the fourth group of outputs of the converter, and the output is with the second output of the converter, the group of outputs of the first register is connected to the second group of outputs of the converter and the second the inputs of the AND elements of the first group, the outputs of which are connected to the group of inputs of the OR element, the output connected to the first input of the converter, the group of inputs of the second register is connected to the outputs of the ntov And the second group, the second inputs of which are connected to the input of the second inverter. .· 4 . The device according to claim 1, characterized in that the comparison unit contains a group of equivalence elements, a group of elements AND, an element AND and an OR element, the first and second inputs of the equivalence elements of the group being connected respectively to the first and second groups of inputs of the block, and the outputs to the first the inputs of the corresponding AND elements of the group, the second inputs of which are connected to the third group of inputs of the block, and the outputs to the group of inputs of the OR element, connected by the output to the first input of the AND element, the second input and output. of which are respectively the input m and output unit. - 1 .