SU1290324A1 - Device for distributing jobs to processors - Google Patents

Abstract

The invention relates to computing and can be used to build multiprocessor computing systems. The purpose of the invention is to expand the functionality of the device by taking into account group failures of processors in the course of solving the problem. The device contains a group of storage registers, a readiness register, a shift register, three groups of AND elements, three groups of AND blocks, an AND element chip, two OR elements, and four OR groups of elements. A new device is the use of a register of processor failures, a buffer register, two groups of AND elements, a group of AND blocks, a group of comparison circuits, a group of delay elements, three delay elements, a mode trigger, a control trigger, an OR-NOT element, two AND, pulse generator and their connections, which ensures the achievement of the objectives of the invention. The device provides high accuracy for any type of processor failure stream. 1 il. WITH/)

Description

fO

11290324

The invention relates to computing and can be used to build multiprocessing computing; systems.

The aim of the invention is to expand the functional capabilities of the device by taking into account group failures of processors in the course of solving the problem.

The drawing shows a block diagram of the device.

The device contains a group of inputs 1 of the device’s order, a group of storage registers 2, a group of elements AND 3, a group of blocks of elements AND 4, a group of blocks of elements AND 5, a group of elements OR 6, a group of elements OR 7, a shift register 8, an element OR-NOT 9 , Element AND 10, group of blocks of elements AND 11, group of elements OR 12, group of information outputs 13 of the device, register 14 - readiness, delay element 15, element OR 16, element OR 17, trigger 18, mode, element 19, element 20 , element And 21, element And 22, group of elements And 23, element And 24, delay element 25, element delay t 26, register 27 bounce protsessoSignalom start trigger 36 is set in state 1 is defined beginning of a cycle of operation.

 The device can operate in one of two modes:

1) the distribution mode of the processors in accordance with the required number of processors indicated in the application,

2) the redistribution mode of the processors when the processor fails in the process of solving the problem.

The allocation mode is set by mode trigger 18.

The first mode starts with the receipt of the application in registers 2 with the subsequent distribution of the processors as follows.

Since register 8 is in the zero state, the AND 3 and 20 elements are open from the output of the OR-NOT element with a single signal. From the zero output of the mode trigger 18, the AND 3, 23, 8, and 24 elements are opened by the corresponding inputs.

If there are ready signals in register 14 with a single signal

J5

25

ditch, group of elements AND 28, buffer element OR 16 open element AND 21, register 29, group of elements AND 30, group of blocks of elements AND 31, group of comparison circuits 32, group of elements AND 33, generator 34 of pulses, group of delay elements 35, trigger 36 control, signal output 37 of the device, input 38 of the start of the device, groups of signal inputs 39, 40 of the device.

The device works as follows.

The initial state of the device is characterized by the fact that the triggers 36, 18, the registers 8, 27, 29 are set to the state O (not shown). In the readiness register 14, the processor readiness signals are received at inputs 40.

Applications for solving the problem, which are generated by the planning system, are sent to a group of inputs 1 of the device, accompanied by a trigger signal at input 38

The application contains the binary code of the task number and the position code of the number of processors needed to solve it in the form of the corresponding number of adjacent units located, starting with the lowest order bit.

the corresponding inputs of the elements And 3 and through the elements And 23 - blocks of elements And 4.

On the first impulse of the generator

35 through the element Pf 21 with the help of the elements AND 3, the input from input 1 is received into those storage registers 2, which correspond to the presence of processor readiness signals in register 14.

40 After some time, determined by the delay element 35, the code of the number of required processors through the corresponding b} 1 of the elements of the AND 5 and the elements 1 of the SHI 7 is transmitted to the register 8

45 cpflura. The delay time by delay elements 35 is determined by the transient processor time in registers 2.

After receiving the code in the 8 shift register, at the output of the OR-NOT 9 for50 element, a zero signal is closed, covering the IZ, 20, 24 elements and opening the And 22 to I 10 elements through the inverse inputs.

Further work depends on the position code of the ready signals in register 14.

If the number of units in adjacent positions of register 14, start with the least significant bit, is greater than or equal to O

f The trigger signal 36 is set to state 1 to determine the start of the device operation cycle.

 The device can operate in one of two modes:

1) the distribution mode of the processors in accordance with the required number of processors indicated in the application,

2) the redistribution mode of the processors when the processor fails in the process of solving the problem.

The allocation mode is set by mode trigger 18.

The first mode starts with the receipt of the application in registers 2 with the subsequent distribution of the processors as follows.

Since register 8 is in the zero state, the AND 3 and 20 elements are open from the output of the OR-NOT element with a single signal. From the zero output of the mode trigger 18, the AND 3, 23, 8, and 24 elements are opened by the corresponding inputs.

If there are ready signals in register 14 with a single signal

five

five

element OR 16 open element AND 21,

the corresponding inputs of the elements And 3 and through the elements And 23 - blocks of elements And 4.

On the first impulse of the generator

through the element Pf 21 by means of the elements AND 3, the input from input 1 is received into those storage registers 2, which correspond to the presence of processor readiness signals in register 14.

After some time, determined by the delay element 35, the code of the number of required processors through the corresponding b} 1 and elements of the AND 5 and the elements of 1 SHI 7 is transmitted to the register 8

cpflura. The delay time by delay elements 35 is determined by the transient processor time in registers 2.

After receiving the code in the shift register 8, a zero signal is formed at the output of the OR-NOT 9 element, covering the elements IZ, 20, 24 and opening the elements And 22 to And 10 in the inverse inputs.

Further work depends on the position code of the ready signals in register 14.

If the number of units in adjacent positions of register 14, starting at the lower order, is equal to or equal to the corresponding number of units of register code 8, then the task number code from storage registers 2 through open elements AND 4 corresponding blocks, elements OR 6 and a group of blocks And 11 enters at the outputs 13. At the same time, single signals from the outputs of the corresponding elements OR 12 set the same-named bits of the fO 8 and 14 registers to the zero state. At the same time, the register B is in the zero state.

If the number of contiguous units in register 8 exceeds the number of contiguous units in register 14 or the number of 15 units in register 14 is equal to or greater than the required number of processors to solve the problem, then these units are placed in register 14 in arbitrary order — and after the like 20 are extinguished. register bits 8 and 14, considered in register 8, bits of bits will remain in a single state ..

In the first case, when all bit one bit in the direction of older bits. If after this shift there is no coincidence of units in the same bits of registers 8 and 14 in the manner described, the next shift of the register code 8 is organized. With the help of the element And 10, the code in register 8 is cyclically shifted by transferring the highest unit to the least significant bit. d.

The cyclic shift process will continue until the required number of processors is assigned. In this case, a single signal from the output of the SHSh-HE element 9 closes the target of the cyclic transfer and ensures that the trigger 36 is set to the zero state.

The second mode of operation of the device is organized upon receipt of signals of failures from the distribution of procedures. These signals are recorded in

register dyes 8 are set to 25 in the corresponding register bits 27

 ABOUT

which means the completion of processor breakdowns.

dividing the processors into a task, the next cycle is organized as follows.

The delayed signal delay elements 25, 26 and 15 through the element And 24 trigger 36 is set to the state O. Single signal

The zero output of flip-flop 36 arrives at the output 37 of the device and is used as a signal that the device is ready for the next distribution cycle.

The next distribution cycle begins after the next input is sent to inputs 1 accompanied by a trigger signal at input 39.

In the second case, when in register 8 all bits are set to the state O, a zero signal is formed at the output of the element OR NONE 9, covering the elements IZ, 20 and 24 and opening And 19 and 33 are opened by inverse.

I will give elements AND 22 and 10. Since the element 50 of the fault signals in register 29, AND 24 is closed, the delayed signal And elements 24, 23, 3 and the distance from the output of the delay element 15 do not change trigger 36. Therefore, the next signal of the pulse generator in the presence of ready signals in the register 14 through the elements 21 and 22, coming to the input

In this mode, the number of failed processors is determined when solving a problem with the same number. This is provided as follows.

register shift control 8, its contents are shifted by

one bit to high bit. If after this shift there is no coincidence of units in the same bits of registers 8 and 14 in the manner described, another shift of the code of register 8 is organized. With the help of element 10, the code in register 8 is cyclically shifted by transferring the higher unit to its lower order.

The cyclic shift process will continue until the required number of processors is assigned. In this case, a single signal from the output of the SHSHE 9 element closes the cyclic transfer target and ensures that the trigger 36 is set to the zero state.

The second mode of operation of the device is organized when signals of failures from distribution of processors are received. These signals are captured in the corresponding register bits 27.

processor failures.

Processor redistribution mode is established by trigger 18.

upon completion of the allocation of processors, i.e. when the shift register is in the zero state, as follows.

In the zero state of the trigger 18

with a single signal from its zero output, elements 28 are opened, it monitors the failure signals in register 29. After register 8 is in the zero state, elements 19 and 20 will open with a single signal from the output of OR-NO 9 generalized signal of failure from the output of the element OR 17 delayed signal with

the output of the delay element 26, the trigger 18 is set to state 1 through the element And 20.

After the trigger 18 is set to state 1, the transmission is blocked

the elements are covered by AND 19 and 33.

Fault signals in register 29, elements 24 and 23, 3 are crashing.

signals of failures in register 29, elements AND 24, 23, 3 are dumped and

In this mode, the number of failed processors is determined when solving a problem with the same number. This is provided as follows.

Through the elements And 30, included in the priority scheme with

register outputs 29, selects the priority processor. At the same time, the smaller number of the register register 29 corresponds to a higher priority.

The selected priority signal allows the transfer of the task number code of the failed processor through the corresponding block of elements AND 31 to the second groups of inputs of the comparison circuits 32. The first inputs of the comparison circuits 32 receive the binary codes of the task numbers from the first output groups of the corresponding storage registers 2

In comparison circuits 32, the task number codes are compared with the task number code of the selected failed processor. At the same time, at the outputs of the comparison circuits 32, a position code of the number of processors assigned to the task with the selected AND 31 elements is generated. With the help of the AND elements from the signals of the comparison circuits 32, the signals of the failed processors recorded in the register are allocated, and same number.

On the next pulse of the generator 34, through the element AND 21, in the presence of free processors, the position code of the number of failed processors through the elements AND 33 and OR 7 is transmitted to the shift register 8. At the same time, the corresponding register bits are set to state O

The distribution of the processors is carried out in the same way as the 1 st.

If after transferring the code of the number of failed processors to the shift register 8 and the allocation of free processors, the register 8 will be in the zero state, then the delayed signal 18 is set to O by the delayed signal from the output of the delay element 25

According to the zero state of the trigger 18, the transmission of the fault signals from the register 27 to the register 29 is enabled. If there are fault signals, then the delayed signal from the output of the delay element 18 is again set to state 1,

In the future, the device operates similarly to the considered mode of processor redistribution.

If there are no signals of failures, then the trigger 18 remains in the zero state, and the delayed signal from the start of the delay element 15 triggers control 36 to the state O, preparing the next processor distribution cycle,

Claims (1)

Invention Formula A device for assigning tasks to processors, which contains a group of storage registers, a ready register, a shift register, four groups of elements AND, three groups of blocks of elements AND, four elements AND, two elements OR, and four groups of elements OR, and groups of information inputs of storage registers GRZ PPA. are a group of inputs of the device's application, the control input of each of the storage registers of the group is connected to the output of the same name element And the first group, the first the group of outputs of each register of storage of the group is connected to the group of inputs of the block of the same name of elements AND of the first group, the second group the outputs of each register of the storage group are connected to a group of inputs of the same name block of elements of the second group, the same names of outputs of a group of outputs of blocks of elements AND of the first group are connected to groups of inputs of the same name. OR of the first group, the outputs of which are connected to groups of inputs of blocks of the third group each: block of which is connected to the group of inputs of the element of the same name OR of the third group and with the corresponding group of outputs of the device, of the same name of the group of outputs of the blocks of the element in the second, the groups are connected to the groups of inputs of the elements of the same name OR of the second group, the outputs of the elements OR, the second group are connected to the group of information the inputs of the shift register, the input of the shift control of which is connected to the output of the first element And, the clock of the shift register is connected to the output of the second element And, etc. my input which is connected to the first output of the group of outputs of the shift register, the first group of signal inputs of the device is connected to the group of information inputs of the readiness register, the group the reset inputs of which are connected to the inputs of the elements of the third group and to the group of inputs of the reset of the shift register, the group of outputs of which is connected to the first inputs of the blocks of elements AND of the third group, the second inputs of which are connected to the same outputs of the ready register, with the corresponding inputs of the first element OR, the first inputs of the elements of the same name AND the first and second groups of the output of the first element OR are connected to the first input of the third element AND the output of which is connected to the direct input of the first element AND, which is so that, in order to expand the functionality by taking into account group processor failures in the course of solving the problem, the processor fault register, the buffer register, the fifth group of elements And, the fourth group of blocks of elements And, the group of comparison circuits, the group of delay elements the delay element, the mode trigger, the control trigger, the element SHI-NOT, the fifth and sixth elements AND and the pulse generator, the output of which is connected to the second input of the third element AND, the third input which is under the keys to the single output trigger and the control, the zero output of which is the signal output of the device, the single control trigger input is the start input of the device, the output of the third element AND is connected to the second inputs of elements AND of the first group, with the first inputs of elements AND of the third group and with the input of the first delay element, output which is connected to the first input of the fourth element And through the second delay element to the first input of the fifth element And to the input. the third delay element, the output of which is connected to the first input of the sixth element AND, the output of the fifth element AND is connected to a single input of the mode trigger, the output of the shift register is connected to the inputs of the OR-NOT element whose output is connected to the inverse inputs of the first and second elements AND to the second the inputs of the fourth, fifth and sixth elements And, and to the third inputs of the elements And the first group, the output of the fourth element And is connected to the zero input of the mode trigger, the zero output of which is connected to ABOUT five 0 five the fourth inputs of elements AND of the first group, to the second inputs of elements AND of the second group, to the first inputs of elements AND of the fourth group and to the second input of the sixth element AND, the unit output of the mode trigger is connected to the second inputs of the elements AND of the third group and to the third input of the fourth element AND The second group of signal inputs of the device is connected to single bit inputs of the register of processor failures, the outputs of which are connected to the second inputs of elements AND of the fourth group, the outputs of which are connected to the single inputs one nominal bits of the buffer register, the unit outputs of which are connected to the inputs of the second element OR, the output of which is connected to the third input of the fifth AND element, the single output of the first bit of the buffer register is connected to the third input of the first AND element of the third group and to the input of the first block of AND elements of the fourth group, the unit output i-ro of the buffer register (, 3, ... n, n is the number of processors) is connected to the first input (i-1) -ro of the element And the fifth group and to the third input of the i-ro element And the third. groups, zero output (i-l) -ro bit of the buffer register is connected to the corresponding to the relevant inputs (1-1) of the (i-2) -ro, ..., (n-1) -th elements of the And p group, output of the j-ro element of the And p group (J-1 .. .n-1) is connected to the input of the i-ro block of elements AND the fourth group, the first group of outputs of each register of the group is connected to the group of inputs of the same block of elements of the fourth group and the first group of inputs of the same name comparison circuit group, the second group of inputs of each comparison circuit group connected to the group of outputs of the same block of elements AND the fourth group, the i-th output of the group of outputs of the block of elements AND the fourth group PPA is connected to the corresponding input of the i-ro element OR of the first group, the outputs of the comparison circuits of the group are connected to the fourth inputs of the same name elements AND the third group, the outputs of which are connected to the corresponding inputs of the same elements OR of the second group and to the zero inputs of the same name 9129032410 register of processors' failures, output of a block of elements AND of the second group, of each element AND of the first group, the steps of the elements AND of the second group of the same-named delay element i dinina with the inputs of the same block of the group are connected to the input of the same name AND of the first group. Editor M. Bandura. Compiled by M. Kudr Shev Tehred A. Kravchuk Proofreader S. Cherni Order 7903 / 47Tirage 673 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 113035 Production and printing company, Uzhgorod, st. Project, 4