SU1319029A1 - Microprogram control device - Google Patents

Abstract

The microprogram control unit relates to computing technology and can be used in the construction of fault-tolerant microprogrammed processors of programmable controllers, computational and control systems with microprogrammed control. The purpose of the invention is to increase the fault tolerance of the device. The firmware control device contains a memory block 1 mxS (L 00 with co with Riz.1

Description

rokomand, group of memory blocks 2.1-2, p nano-commands, address forming unit 3, command register A, address registers 5 and 7, buffer register 6, nano-command register 8, control units 9 and 10, switching unit 11, commutators addresses 12, 13 and 14, multiplex131

one

The invention relates to computing and can be used in the construction of fault-tolerant microprocessor processors, programmable controllers, computational and control systems with microprogrammed control.

The aim of the invention is to increase the resiliency of the device.

FIG. 1 is a functional block diagram of a firmware control device; in fig. 2 - functional diagram of the first control unit; Figo 3 is a functional diagram of the second control unit; 4 is a functional block diagram of an address generation unit; in fig. 5 - functional circuit of the switching unit; FIG. 6 is a functional diagram of a code converter; FIG. in fig. 7 illustrates an example of forming a three-syllable nano-command with a switching unit.

 The microprogram control unit (Fig. 1) contains a block of 1 memory of micro-commands, a group of blocks 2.1-2. V modifiable bit of address 6 2 2, unmodifiable bits of address 6.3, address of nano-command 6.4, sign of parity of information 6.5., Second register 7 of address, register 8 of nano-commands, first control unit 9, second control unit 10, switching unit 11, the first switch 12 addresses, the second switch 13 addresses, the third to 14 mmutator address multiplexer logic 15 conditions unit 16 of AND gates 16, 17 start trigger, the trigger 18 failure, clock generator 19, the block elements 20, NOT 20, the first AND gate 21, the second AND gate 22, tre1319029

logic conditions 15, block of elements AND 16, trigger 17 of start, failure trigger 18, generator of 19 clock pulses, block of elements NOT 20, four elements of AND 21, 22, 23 and 24, two elements of OR 25 and 26, single vibrator 27 .7 ill.

five

about

five

0

five

0

And 23, the fourth element is And 24, the second element is OR 25, the first element is OR 26, the one-shot 27, information input 28 of the device, input 29 of the start-up of the device, input 30 of the logical and information outputs 31 of the device.

The first control unit 9 (Fig. 2) contains the element 32 of the sum modulo two, the counting trigger 33, the first single vibrator 34, the second 35 and the third 36 one-oscillators, the first element And 37, the second element And 38 and the delay element 39.

The second control unit 10 (FIG. 3) contains a modulo two element 40, an error counter 41, a decoder 42, a one-shot 43.

The address generation unit (an example of implementation on 1SM, Fig. 4) contains a group of inverters 44.1-44.t, the first 45.1-45op and the second 46.1-46.t group of resistors.

Switching unit 11 (Fig. 5) contains there is a block of converters 47.1-47.p codes (where n is the number of nano-team syllables), a group of blocks 48.1-48.

In addition, the i-th (, p) converter of codes 47.1 (Fig. 6) contains a decoder 49 and a group of blocks 50.1-50.

The essence of the invention is as follows. The firmware is divided into two channels; address and operational. Each channel contains a corresponding memory block: in the address memory block of micro-instructions, in the operational one there is a memory block of nano-commands. Nano-teams interpret microcommands. Splitting a device into two channels allows you not to have a fixed set of micro-commands, since the action of a micro-command is completely determined by its interpretive nano-program. In this case, the memory block is divided into n blocks, which increases the flexibility of forming nano-commands (operational micro-instructions) based on the concatenation (concatenation) operation of the individual syllables of the controlled word. Each channel (memory block) is controlled separately: the output words are controlled by parity, (oddness). If an error is detected in the address channel when reading a microcommand, the operation channel is blocked and the microcommand memory block is re-addressed at the inverse address that stores a copy of the microcommand. If an error is also detected at the inverse address, a failure signal (symptom) is generated. In the operation channel, when an error occurs, the address is dynamically changed and the individual syllables of the nano-command are reconfigured.

Consider the ra: bot firmware control device. In the initial state, the memory elements of the device are in the zero state (with the exception of the register trigger 8 nano commands, which determines the end of the device operation).

The current command from the control bus is fed to the input 28 of the device and entered into the register of 4 commands (synchronization signals not shown). The signals determining the operation code are transmitted through the address switches 12 and 13 to the information input of the address register 5

The start of operation of the device is determined by applying a pulse from the input 29 of the device. According to this pulse, the trigger 17 goes into a single state and thereby enables the formation of pulses from the output of the generator 19 for organizing synchronous operation of the device. By the first clock pulse, the address code of the first microcommand is entered into the address register 5. At this address, information is sampled from block 1 of the micro-instructions, and the connected micro-command is entered into the buffer register 6 by the second clock pulse.

If an error control unit 9 is not detected in the read-through micro-command, the address of the nano-command from the floor 6.4 of the buffer register 6 via the address switch 14 is sent to the information input of the register 7 address and the third pulse is entered into the address register 7. From the group of blocks 2.1-2. The memory of nano-commands are counted among the syllables of the nano-command that arrive at the information inputs of the switching unit 11. Since a zero code arrives at the control input of the switching unit 11, the individual syllables of the nano-command without their rebuilding (reconfiguration) by the fourth clock pulse are entered into the register of 8 nano-commands.

If block 10 of the control unit does not detect an error in the generated nano-command, the output of the register of 8 nano-commands through the block 16 of the elements AND the nano-command enters output 31 of the device.

If the next microinstruction is a microinstruction of a linear sequence, its address is determined by the contents of field 6.3 of the buffer register 6 of the unmodifiable address bits.

If the selected micro-command is a branch micro-command, the modified address bit from the output 6.2 of the buffer register 6 is modified by the logic conditions from the input 30 of the device at the multiplexer 15 logical conditions.

If an error is detected by block 9 in the selected microcommand in parity checking, blocking the operation channel and accessing microcontrol memory block 1 at the inverse address.

If an error is not detected at the inverse address in the microcomputer read by block 9, the trigger 33 errors (Fig. 2) goes to the zero state.

Block 9 control functions as follows. The microcommands read from block 1 are controlled by the element 32 of the modulo two evenness (oddness).

If the controlled signs do not match, a pulse is generated at the output of the one-shot 34, which sets the trigger 33 for errors into a single state (when the microcommand is read at the direct address). When the flip-flop 33 goes to the single state -: che at the output of the one-shot 35 for513

A symptom of an error is detected. At the same time, when determining the presence of an error in the considered micro-command, the pulse from the output of the one-shot 34 arrives at the input of the delay element 39. If an error is detected and at the inverse address (the error trigger 33 goes to the zero state), then the output of the one-shot 36 produces a pulse that arrives at the output of the And 37 element, forming the indication of the failure of the address channel. If the inverse address has an error in the microcommand until module two is detected (trigger 33 is erroneous and in one state), the pulse from the output of delay element 39 through AND 38 zeroes the error trigger 33 of control block 9. When block 9 detects the control of the sign of a failure of the address channel, this sign sets the trigger 18 for a failure to one state through the IL 26 element. At the output of the one-shot 27, a pulse is formed, which through the element OR 25 sets the trigger 17 for the start state to zero, and the device finishes the operation.

If an error is not detected at the inverse address in the microcomputer read by block 9 of the control, the device continues to function.

The address of the nano-team from the floor 6.4 of the buffer register 6 through the address switch 14 is fed to the information input of the register 7 address. Upon receipt of a clock pulse from the output of the generator 19 through the AND 23 element to the synchronizing input of the register 7 address, the address of the selected nano-command is entered into register 7. Through the next clock pulse, the counted syllables of the nano-command are switched to the register 8 by the switching unit 11. The control unit 10 monitors the counted information on parity (oddness). If no error is detected, then the nano-command from the output of the register 8 through the block of elements AND 16 enters the output 31 of the device to control, for example, an arithmetic logic unit or another operational block.

If an error is detected in the numbered nano-command, the control unit 10 generates an indication of an error. This feature prohibits the issuance of a selected nano-team to manage operating

96

block and block the address channel by prohibiting the passage of clock pulses through the elements 21 and 22 to the clock inputs of the register 5

addresses and buffer register 6.

When determining the control unit 10 (Fig. 3) errors in the nano-command, the state of the error counter 41 is different from zero. This code arrives at the control input of block 3. The address code of the nano-team from field 6.4 of the buffer register 6, being input to the information input of block 3, is modified. The modified code of the nano-command address through the address switch 14 is entered into the address register 7. In addition, from the output of unit 3 to the control input of the switching unit 11, the setting code is received.

It is a procedure for rebuilding individual syllables of a nano-team when forming a control word.

If no error is detected in the current nanocand, the nanocand through the element block 16 And enters the output 31 of the device, which continues to function as described.

With the latest Nano-Team

an indication of the end of operation of the device is given, which through the OR element 25 sets the trigger 17 to the zero state and through the address switch 12 allows the new operation code to be overwritten from the output of the register of 4 commands for its further conversion.

The address generation unit 3 implements the address formation (function) with

using a programmable logic matrix (W1M).

Block 3 is designed to modify the address when a failure occurs in blocks 2.1-2.p of the memory of the operation channel

The code of the number of failures is formed in the control unit 10 and is fed to the control input of the unit 3 (Fig. 1). In the case of a zero code, the modification of the address code in block 3 does not fail, and the control input of the switching unit 11 receives a zero code.

The inputs of the associative memory block receive the address code of the nano-command (codes of syllables of the nano-team) and the failure number code 0. With this information, the block of associative memory forms the address codes of the next syllables of the nano-command and the setting code

restoring syllables during the formation of a nano-team in the I 1 switching unit.

Claims (1)

Invention Formula A microprogram control unit containing a memory block, micro-commands, a group of nanocommand memory blocks, three address switches, two control blocks, a command register, two address registers, a buffer register, a logic conditions multiplexer, a register of nano-commands, a block of AND units, a block NOT elements, trigger trigger, clock pulse generator, failure trigger, four AND elements, two OR elements, one-shot, and the device information input is connected to the command register input, the output of which is connected to the first information input th first switch addresses, device start input is connected to the trigger input unit zapus ka, my output is connected the clock pulse is connected to the direct input of the third element I, the output of which is connected to the synchronizing input of the second address register, the field outputs of which are connected to the address inputs of the corresponding memory blocks of the nano commands, the fourth output of the clock generator is connected to the direct input of the fourth element I , the output of which is connected to the sync input of the nano-command register, the output of the first address switch is connected to the first information input of the second address switch and the input block and NOT elements whose output is connected to the second information input of the second address switch, the output of which is connected to the information input of the first address register, the output address field of the nano-command of the buffer register is connected to the first information input of the third address switch whose output is connected to the information input of the second register addresses, outputs of the logic conditions code field, fields of unmodifiable address bits, address fields of the nano-command of the buffer register are connected to the information input of the first block and the contros input of the start of the clock pulse generator, the first output of which is connected to the direct input of the first element I, the output of which is connected to the clock input of the first address register, the output – first address register is connected to the address input of the microcommand memory block, the output of which is connected to the information input of the buffer the register, the output of the control unit field 35 is connected to the direct and logical conditions code of the buffer inverted control inputs of the second f hystera is connected to the control input of the multiplexer of logic conditions, the output field of the modifiable bit of the address of the buffer register is connected to the first in-40 control unit connected to the first inputting input of the multiplexer by the first element OR, the output of the cogical conditions, the output field unmodifiable address bits of the buffer register are connected to the input of unmodifiable i bits of the address of the second information generator 45, the output of which is connected to the first input of the first switch by the address of the first input of the second OR element, l, the output of the parity flag of the buffer register is connected to the input of the definition of the first control unit, the output of the error sign of the first switch address and inverse inputs of the third and fourth elements And the output of the sign of failure of the first which is connected to the single input of the failure trigger, the direct output of which is connected to the single-input trigger input, the output of the logical conditions multiplexer is connected to the input of the modified address bit of the second information input of the first address switch, the logical conditions input of the device is connected to the second information input of the logical conditions multiplexer, the second the output of the clock pulse generator is connected to the direct input of the second element I, the output of which is connected to the clock input of the buffer register, tert th vyw five  5 20 I90298 the clock pulse is connected to the direct input of the third element I, the output of which is connected to the synchronizing input of the second address register, the field outputs of which are connected to the address inputs of the corresponding memory blocks of the nano commands, the fourth output of the clock generator is connected to the direct input of the fourth element I , the output of which is connected to the sync input of the nano-command register, the output of the first address switch is connected to the first information input of the second address switch and the input block and NOT elements whose output is connected to the second information input of the second address switch, the output of which is connected to the information input of the first address register, the output address field of the nano-command of the buffer register is connected to the first information input of the third address switch whose output is connected to the information input of the second register addresses, outputs of the logic conditions code field, fields of unmodifiable address bits, address fields of the nano-command of the buffer register are connected to the information input of the first block and kontro25 35 of the control unit is connected to the direct and inverse control inputs of the second the control unit is connected to the direct and inverse control inputs of the second l, the output of the parity flag of the buffer register is connected to the input of the definition of the first control unit, the output of the error sign of the first the control unit is connected to the first input of the first OR element, the output of the switch address and inverse inputs of the third and fourth elements And the output of the sign of failure of the first the control unit is connected to the first input of the first OR element, the output of the the second is connected to the single input of the failure trigger, the direct output of which is connected to the launch input; the single output of which is connected to the zero input of the trigger trigger, the output of the information field of the register of nano commands 50 is connected to the information input of the AND block and the information input of the second control block, the output of the gender of the parity attribute of the register of nano commands is connected to the input of the sign 55 parity of the second control unit, the output of the error indication of which is connected to the inverse control input of the AND element block, inverse inputs of the first and second AND elements, inverse and direct control inputs of the third address switch, the output of the failure sign of the second control block is connected to the second input of the first the OR element, the output of the sign of the end of operation of the block of elements AND is connected to the second input of the second element OR, the forward and inverse control inputs of the first address switch, the operational outputs of the block of elements And connected to informational outputs of the device, characterized in that, in order to ensure high stability, it further comprises an address generation unit and a switching unit, the output of the address field of the buffer register nocomand is connected to the information input of the address generation unit, the output of which is connected to the second information input the third switch and the control input of the switching unit; the outputs of the memory blocks of the nano-commands of the group are connected to the corresponding information inputs of the switching unit; the outputs of the After the switching is connected to the information inputs of the corresponding bits of the nanocommand register, the output of the setup code of the second control unit is connected to the control input of the address generation unit. 40 R - -y 42 Fl / a. H . 47 / "E ff7.2 iun four e A / g5 " 2.6 Editor O. Bugir Compiled by D. Vanyukhin Tehred M. Khodanich Proofreader G. Reshetnik Order 2513/43 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4