SU943736A1 - Microprogram data processing system - Google Patents

Description

(54) FIRMWARE TREATMENT SYSTEM

DATA

one

The invention relates to computing technology and is intended for use in control systems of digital computers with; microprogrammed control, for example, in modular microcomputers containing several identical or different LSIs intended for converting information, and one or several LSIs forming a microprogrammed control device. Jq

The firmware data processing units and firmware control devices are known, which contain one information conversion unit, a memory, registers, descriptors and control circuits i.

The disadvantages of these devices are inefficient use of microprogram memory and loss in speed, due to the fact that with these -20 transitions it is necessary to delay the selection of the next microcommand until the execution of the current microcommand is completed and the result features are generated.

Closest to the proposed technical.-Entity, is a microprogram data processing system, the use of which allows to increase the speed of the device and the efficiency of using microprogram

memory xi

The system contains several information conversion units, each of which has a condition bus connected to the corresponding input of the microchip sequence control block (dand. The control inputs of the blocks are connected to the outputs of the demultiplexer, whose information input is connected to the output of the microprogram memory block. The microprogram memory input is connected to the output of the register of the address, which is also connected to the input of the block. The outputs of the bits of the cyclic. shift register are & adventured to the control of the 39-1 inputs of the demultill The XORO and the control unit sms follow the sequence of the cyclic commands. IIpiHHiran system operation consists of the following: From the microprogram memory block, which stores the MUKponporpaMNdbi, which the blocks will work to convert information, at constant time intervals specified by the synchro shzatt circuits, read the microchip microscopic information, at a time interval specified by the synchro shzatt circuits, read the microchip microscopic information in the microchip memory. Each microinstruction from the output of the block is fed to the input of the demultiplexer, and then to the input of the information conversion unit, to which the resolving value of a certain register bit corresponds and corresponds control input of the demultiplexer. In the corresponding block, a microinstruction begins to work. By entering the microcontroller sequence control block control input, the same register resolution value allows the block to generate the next address for the microcommand of the next block, for which the conditions of the n: headspace microcoin command are displayed on its condition bus. The address generated by the block, depending on the value of the contents of the address register and the signs of the conditions on the bus, is transmitted to the address register, a shift is made in the register, and a new microcommand appears at the outputs of the microprogram memory. Thus, several information conversion units are controlled from a common microprogram memory unit in a time division mode. If the processing of information can be parallelized between several processing units or if the information conversion units operate on independent firmware, then the described system can improve the overall speed and increase the efficiency of using the microprogram memory, as time is reduced due to downtime in the case of conditional transitions. Indeed, the firmware memory does not wait for signs of the result of the operative, as is the case with one information conversion unit, but it does issue a microcommand for another block 2. However, the known device has the following disadvantages. The order and sequence of the information conversion blocks is strictly determined by the sequence of issuing the enabling signals of cyclic-ktgm shift register. In fact, a micro-command can be sent only to one information conversion unit, thereby eliminating the exchange of information between the blocks and the simultaneous control of several blocks. In addition, in a known device, microcommands from microprogram memory are read at constant time intervals that are equal to the microprogram memory cycle and do not lead to its idle time only when the ratio between the microprogram memory cycle is correctly selected, if the execution time of microinstructions in different blocks is the same. Otherwise, the indicated time intervals are chosen based on the speed of the slowest information conversion unit, which reduces the speed of the system. The purpose of the invention is to increase functionality and increase speed. This goal is achieved by the fact that a device containing a group of v-bathing blocks, a microprogram memory block, a control block, a switch, the inputs / outputs of the processing blocks of the group are the inputs of the system, the first outputs of the processing blocks of the group are respectively connected to the group of inputs of the block control, and the inputs of the processing units of the group are connected respectively to the outputs of the switch, the information input of which is connected to the output of the microprogram memory block whose input is connected to the output control block, a group of trigger triggers, a group of control triggers, the first and second groups of elements AND, the OR element are entered, the second and third outputs of the group processing blocks are connected to the inputs of the corresponding group trigger triggers, the first outputs of the group trigger triggers are connected to the first the inputs of the corresponding elements of the first group, and the second outputs of the trigger triggers of the group are connected to the first inputs of the corresponding elements of the second group, with the second inputs of the elements of the first and second groups The pins are connected to the outputs of the corresponding group control triggers, the outputs of the elements of the first group are connected to the inputs of the element OR, the output of which is connected to the first control input I of the control unit, the outputs of the elements of the second group are connected to the inputs of the switch and the second control inputs of the control unit, and The control trigger inputs of the group are connected to the outputs of the microprogram memory block. The scheme of the proposed microprogram data processing system is shown in the drawing. The group of processing units 1 is interconnected by a data bus 2. A suppressing input, 3 of each processing unit 1 is connected to the corresponding output of switch 4, and the current inputs 5 and 6. The inputs 5 are connected to the outputs of elements AND of the second group 7, and input 6 connected to the first output of the microprogram memory 8, having the second outputs 9 associated with the installation inputs of the control group trigger 10. The output of each trigger of the control group 1O is connected to the second inputs of the corresponding elements And 7 and elements 11, the first inputs of which Switched to the unit and zero outputs of the trigger of group 12, respectively. The group of trigger triggers have zero and one setting 1 move1, connected to the corresponding outputs of the processing unit 1. The outputs of the And 7 elements are also connected to the corresponding control unit inputs (sequence of micro-commands) 13 having a blocking input associated with the output of the element OR 14. The inputs of the element OR 14 are connected to the outputs of elements AND of the first group 11. Each processing unit has a condition bar 15, connected To the corresponding inputs of the microprocessor sequence control unit 13, the output of which is connected to the input of the microprogram memory block 8. Synchronization circuits, as well as the bus connecting the microprocessor sequence control unit input and the microprogram memory block output, which includes, besides the drive , the decryption schemes and the address register are not shown in the drawing. The proposed microprogram data processing system works in the following way. From the micro-command sequence control unit 13, the micro-command address is supplied to the microprogram memory block 8. At the interval of time necessary for reading information from the microprogram memory block 8, at the outputs of the latter information appears, which consists of two parts. The first part is a micro-command arriving at information input 6 of switch 4. The second part contains the number of bits equal to the number of processing blocks 1. The signal from each bit of output 9 enters the input of the corresponding trigger of the control group 10 and sets it to corresponding to the value of the specified bit. If trigger 10 is set to 1, then its single output at unit state of trigger 12 opens element 7, thereby allowing microinstruction through switch 4 to control inputs 3 of the corresponding processing unit 1. If trigger U is set to O element AND 7 at input 5 of switch 4 prohibits the passage of a microcommand to input 3. The permissive signal from the output of element AND7 entering the input of the control unit of the sequence of microcommands 13 allows the formation and reading of the next microcom Wda whose address is generated, starting from the address portion of a previous microinstruction or soderzh1a1ogo address register and status conditions .ni bus 15 the processing unit 1, which at this time finishes execution its macro. If you specify a unit in one additional bit of the corresponding micro-command, and in the remaining fields, then this mtasro-command controls only the corresponding 11M processing block 1. If the processing of information can be parallelized between several processing units or if the processing units can work on independent microprograms, Then, setting the units in different bits of the microinstructions of the corresponding microprograms can be controlled by several processing units 1 from a common microprocessor block gram memory 8 in time sharing mode. Since, in this case, the firmware memory does not wait for indications of the result of the operation during conditional transitions, but produces a microcommand for another block, time losses due to memory idle times are reduced and the speed is increased compared to systems with a single processing unit. Since, in the general case, the processing units 1 can be different in fuzzyu- nal capabilities, as well as in speed, by the time the m1-g command is issued in some block 1, it may appear that it has not completed the execution of the previous microcommand. To prevent this from happening, at the time when some processing unit 1 began to work by entering Shuya on it to the input to the microcommand, an occupation trigger 12 is set to O in the installation input, which is set to 1 after completion of the microcommand. If the ira output of the microrobe of the amine memory appears from the microcommand belonging to block 1, an occupancy trigger of which is at zero, the output of the AND 11 element appears from the OE signal, which through the OR element 1 blocks the issuance of the next microcommand. Thus, the previous microinstruction at the outputs of the block of firmware memory 8 does not disappear, but enters the selected block as soon as trigger 12 is set to 1. At this point, the blocking of the output of the And 11 element is released and the And 7 element opens. through which the microprogram memory 8 is accessed, are not divided by the slowest processing unit, but by. at least the average speed of the processing units included in the sio topic. Due to this, the speed of the systems is improved. If you specify a unit in several bits at once, appearing at the outputs 9 of the microprogram memory block, the read micro-command is fed simultaneously to several processing blocks 1 at the same time. This is necessary in cases where the indicated blocks are processed in parallel, for example, the major and minor bits of the information (increment by size), when there are special microcommands that provide information exchange between blocks 1 on the data bus 2, when the same microcommand interpreted differently by different processing units 1 due to their setting (by switching external connections or applying residual control), etc. Thus, the indication in the microcommand of one or several processing units One of them allows controlling the sequence of operation of unit 1, controlling their simultaneous operation (if necessary) and, consequently, increasing the functionality of the proposed system in comparison with the known ones. The proposed microprogram data processing system is used in an ICE computer executed on large integrated circuits. Fomula of the invention A microprogram data processing system comprising a group of processing units, a micropower frame memory unit, a control unit, a switch, the inputs / outputs of the processing units being a group. system inputs, the first outputs of the processing units of the group are connected respectively to the group of inputs of the control unit, and the inputs of the processing units of the group are connected respectively to the outputs of the switch, whose information input is connected to the output of the microprogram memory unit, the input of which is connected to the output of the control unit, In order to improve speed, a group of busy triggers, a group of control triggers, the first and second groups of AND elements, the OR element, The third outputs of the processing units of the pear are connected to the inputs of the corresponding group trigger, the first outputs of the group trigger are connected to the first inputs of the corresponding AND elements of the first group, and the second outputs of the group trigger triggers are connected to the first inputs of the corresponding, AND group II elements, while the second inputs of the elements of the first and second groups are connected to the outputs of the corresponding group control flip-flops, the outputs of the elements of the first group are connected to the inputs of the element OR, the output of the cat cerned connected to a first control input of control unit, the outputs of AND gates of the second group are connected to the inputs of the switch and the second control inputs of the control unit, and the control inputs of the group of flip-flops connected to outputs of the microprogram memory block. Sources of information taken into account in the examination 1. USSR author's certificate number 342380, class, G, 06 F 9/00, 1968. 2. US patent number 3689895, class. 342-172.5, 1972 (prototype).

Claims (1)

SUMMARY OF THE INVENTION A microprogram data processing system comprising a group of processing units, a microprogram memory unit, a control unit, a switch, the inputs and outputs of the processing units of the group being. system inputs and outputs, the first outputs of the processing units of the group are connected respectively to the group of inputs of the control unit, and the inputs of the processing units of the group are connected respectively to the outputs of the switch, the information input of which is connected to the output of the firmware block, the input of which is connected to the output of the control unit, distinguish I mean, in order to improve performance, a group of employment triggers, a group of control triggers, the first and second groups of AND elements, an OR element, and the second and the third outputs of the processing units of the group are connected to the inputs of the corresponding group employment triggers, the first outputs of the group employment triggers are connected to the first inputs of the corresponding elements of the first group, and the second outputs of the group employment triggers are connected to the first inputs of the corresponding elements of the second group, while the second inputs of the elements Both the first and second groups are connected to the outputs of the corresponding group control triggers, the outputs of the AND elements of the first group are connected to the inputs of the OR element, the output of which о connected to the first control input of the control unit, the output of elements And the second group are connected to the inputs of the switch and the second control inputs of the control unit, and the inputs of the control triggers of the group are connected to the outputs of the microprogram memory.