SU1195364A1 - Microprocessor - Google Patents

Abstract

MICROPROCESSOR, arithmetic logic unit, dual-channel random access memory with random access, block of exchange registers, scaling block, microcommand memory, command counter, input multiplexer, output demultiplexer, digital-analogue converter and comparator, and a synchronous process module. commands, the output group of which is connected to the group of address inputs of the microinstructions memory block, the output of the micro-operation code of which is connected to By the operation code of the arithmetic unit, the first and second information inputs of which are connected respectively to the output of the scaling unit and to the first output of a two-channel random access memory, the second output of which is connected to the information input of the scaling unit, the control input of which is connected memory microinstructions, the first and second address outputs of which are connected respectively to the first and second address in the two-channel onepaiHBHoro random-access memory device, the first and second information inputs of which are connected to the output of an arithmetic logic unit, the information input of analog signals of the microprocessor connected to the information input of the input multiplexer, the first control input of which is connected to the first control input of the output demultiplexer I / O control field of the microinstructions memory block, the input multiplexer output is Soe (Linden with the first input the comparator house, from: the second input of which is connected to the output of the digital-to-analog converter and the information input of the output demultiplexer, the outputs of which are the outputs of the microprocessor; a digital-to-analog converter, characterized in that, in order to extend the functionality by implementing a processing mode, in addition to analog digital signals, it It contains a mode decoder and three switches, with the first and second information inputs of the first switch connected to the corresponding bits of the output field of the I / O control information module of the microcommand memory, the control inputs of the first, second

Description

, and the third switches are connected to the output of the mode decoder, the first and second inputs of which are connected to the second and third control inputs of the output of the demultiplexer, respectively, and are the first and second inputs of the microprocessor information, output; register block exchange is connected to: the information input of the second switch, the code of which is connected

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with the second control input of the input multiplexer, the third control input of which is connected to the output of the first switch, the information input of the microprocessor digital signals is connected to the first;. the information input of the third switch, the second information input of which is connected to the output of the comparator, the output of the third switch is connected to the information input of the block of exchange registers.

The invention relates to computing, in particular to devices for digital processing of analog and digital signals.

The purpose of the invention is to expand the functionality by implementing a processing mode, in addition to analog digital signals.

The drawing shows the proposed scheme, the microprocessor.

The microprocessor contains an arithmetic logic unit 1, a two-channel random access memory 2, a scaling block 3 of memory A of microinstructions, a command counter 5, an exchange register 6 block, an input multiplexer 7, an output demultiplexer 8, a comparator 9, the third 10, the second 11 and the first 12 switches, mode decoder 13, digital-to-analog converter 14, synchronous switch 15, information input 16 of analog signals, information input 17 of digital signals, first 18 and second 19 inputs of information input-output control, outputs 20, output 21 ode memory operation microinstruction control output of the memory 22 by scaling microinstructions first 23 and second address 24 outputs memory output 25 and microinstruction control field information input-output memory microinstruction.

The microprocessor works as follows.

A program is recorded in the memory of 4 microcommands. Memory 4 micro-instructions controlled by meter

5 commands internal or external clock signal.

The main clock signal is divided into several

phase tantum signals for internal microprocessor synchronization. Counter 5 teams at the same time provides an increase on one account of teams with four cycles of the main clock

signal and considers further to

until it reaches a numerical value equal to the capacity of memory 4, since it is not moved back by the command End of program

or a return signal.

During operation of the microprocessor, the instruction counter 5 sequentially accesses each of the micro-instructions. Transitions to the D program in this case are not applicable.

According to the signals from the corresponding outputs of the memory 4, operands from the two-channel memory device 2 are read out and transmitted directly or via the scaling unit 3 to the arithmetic logic unit 1.

The memory cells in the dual-channel storage device 2 may

simultaneously addressed for transmission on both the first and second outputs. This allows the supply of different operands from one memory device without two separate address cycles.

Over the incoming operands A and B, the arithmetic logic unit produces a number of known

31

operations specified from the output of 21 memory 4 micro-commands. Systems of commands and operations are similar to the well-known yci ™ realm.

The input-output mode of information does not require digital commands, but is carried out through analogue instructions on the external control inputs of the output demultiplexer 8. In the presence of the selected combination of input signals, the decoder 3 has

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switches 10 and 12 one of the inputs of the input multiplexer 7 and the input 17 of the microprocessor to the information input of the two-channel storage device 2 and using the switch 11 controls the multiplexer 17, as a result direct access to the memory is formed, and input-output 1 The th bit of the information to OS1) is in effect for the execution time of one microcommand.

Claims (1)

A microprocessor containing an arithmetic logic device, a two-channel random access memory, a block of exchange registers, a scaling unit, a memory block of microcommands, a command counter, an input multiplexer, an output demultiplexer, a digital-to-analog converter and a comparator, and the microprocessor's sync input is connected to the counting input of the counter the group of outputs of which is connected to the group of address inputs of the memory block of microcommands, the output of the microoperation code of which is connected With the input of the operation code of the arithmetic device, the first and second information inputs of which are connected respectively with the output of the scaling unit and with the first output of the two-channel random access memory with the second output of which is connected with the information input of the scaling unit, the control input of which is connected to the output of the control unit scaling microcommand memory, the first and second address outputs of which are connected respectively to the first and second address inputs random access memory device, the first and second information inputs of which are connected to the output of the arithmetic logic device, the information input of the analog microprocessor signals is connected to the information input of the input multiplexer, the first control input of which is connected to the first control input of the output demultiplexer and the output of the control field input / output information of the memory block of microcommands, (8 the output of the input multiplexer is connected to the first input of the com a parator, the second input of which is connected to the output of the digital-to-analog converter and the information input of the output demultiplexer, the outputs of which are the outputs of the microprocessor, the output of the sign of the exchange of the memory block of the micro-commands is connected to the address input of the block of exchange registers, the output of which is connected to the input of the digital-to-analog converter, characterized in that, in order to expand functionality by implementing a processing mode, in addition to analog, digital signals, it additionally contains a mode decoder an imma and three switches, the first and second information inputs of the first switch being connected to the corresponding bits of the output of the control field of the input-output information of the micro memory command block, the control inputs of the first, second Mila Yam with the next health 4 ^ *. And the third switches are connected. To the output of the mode decoder, the first and second inputs of which are connected respectively to the second and third control inputs of the output demultiplexer and are the first and second inputs of the microprocessor information input-output control, respectively, the output of the register block exchange is connected to r 'information input of the second switch, the output of which is connected to the second control input of the input multiplexer, the third control input of which is connected to the output of the first switch, ormatsionny input digital signal microprocessor connected to the first data input of the third switch, a second data input coupled to an output of the comparator, the third switch output is connected to data input registers exchange unit.