SU1462339A1 - Microprogram processor - Google Patents

Abstract

The invention relates to computing and can be used to build high-speed microprocessor processors with dynamic microprogramming. The purpose of the invention is to expand the field of application of the microprocessor processor by integrating it with another computer. Microprogrammer 1st processor contains blocks 1 and 2 of RAM, block 3 of microprogram memory, switch 4 micro-commands, register 5 micro-commands, switch 6 data, block 7 forming the address of micro-commands, decoder 8 control signals, arithmetic logic unit 9, register 10 commands and block 11 control. ki 4 il.

Description

The invention relates to computing technology and can be used to build high-speed microprocessor processors with 5 dynamic microprogramming. The aim of the invention is to expand the scope of application of the microprocessor processor due to the possibility of its integration with other computers. fO

FIG. G presents the scheme of the proposed microprocessor processor; in fig. 2 is a schematic of the control unit in FIG. 3 is a block memory block diagram; in fig. 4 is a diagram 15 of the data switch.

The microprocessor software processor contains (Fig. 1) blocks 1 and 2 of the RAM, block 3 of the microprogram memory, switch 4 of micro-commands, re-. 20 gistr 5 microinstructions, data switch 6, block 7 for the formation of the address of microinstructions, a decoder 8 control signals 1x signals, an arithmetic logic unit 9, a command register 10 and a control block 11 for 5. The control unit 11 (Fig. 2) contains the address switch 12, the ele., - delay ment 13, the switch 14, the equalizers, the elements 15 and 16, the trigger 17 and the 18 clock pulse generator, the address ty register , element 41LI 20, element EXCLUSIVE OR 21 and address decoder 22, ele-. ment and 23.

Chunk 2 of the RAM contains 35 drive 24 of the most senior word and store 25 of the older word. Block 2 Contains also the address switch 26, the first 27, the second 28, 29 ,. the fourth 30 elements AND, the element NOT 31 40 elements OR 32. The accumulators 24 and 25 form the accumulator 33.

On. Fig. ..- 4 shows an example of a k6mmut scheme, a torus of data that contains the element HE 34 and the element E 35 element 45 And 36-42 with three-stable outputs, element 43 NOT.,

Consider the operation of the firmware processor. It can work in two modes: processing mode and,. Loading mode - The mode of operation is specified by the contents of the register of 10 commands, in which information1 is entered on the information input of the microprocessor processor under the action of the control signal from the UHF output unit 11 when applied to its AHZ, UX4 and UX5 inputs respectively, the addresses of this register, the recording signal and

signal reversal. In download mode, the corresponding register bit 10 at the input AX6 of unit 11 places it in a state in which reception and execution of microcommands from blocks is prohibited. 2 and 3 and the exchange of information of blocks 1 and 2 of the working memory through the bidirectional information input AND 4 of the switch 6 is permitted at the address on the address input of the microprogrammed processor. In this case, data is recorded in block 1, and microprograms are recorded in block 2.

Writing to block 1 is as follows.

The inputs corresponding to the AHZ, UX4 and UX5 of block 11 receive the address corresponding to the address space of block 1, the recording and reversing signals. As a result, the address is sent to block 1 from the code of code 11 of block 11, and from the output of the UVZ a signal is sent to write. Thus, the switch 6 permits the transfer of information from the information input of the microprocessor processor to the information input of block 1, and the information is recorded. After the time interval required for recording the information, unit 11, from its UHF output, transmits a signal of the end of the operation to the output of the microprocessor processor. The information from block 1 is read in the same way. In this case, in block 1 and on; The input of the UHZ switch 6 receives a reading signal that permits the transfer of information by the switch 6 in the opposite direction. .

The difference-appeal to block 2 is that the address and read and write signals come directly from the address and control inputs of the processor, respectively, to address AX2 and control YX2 - the inputs of block 2. At the same time, the access enable signal defined by the value address code, is produced by block 11 and is fed to the control input of the UHZ unit: -2. The same signal received at the control input UX5 of the switch 6, together with the read or write signals at the control input UX2 and the low-order bit value of the address at the control input UX2 of the switch 6, determine its operation. S depending on the value of the lower bit of the address; the switch 6 commutes the information input of the microprocessor processor with the input of the higher one.

31462339

or low word block 2 having

to l

double bit, i.e. with its information inputs I1 or I2.

In the processing mode, the corresponding register bit 10 at the input of the AHb of the block 11 transfers it to a state in which the microcommands from blocks 2 and 3 are allowed to be sampled and loaded and the input from the microprocessor processor to the microprogram 2 is prohibited. Reversal to block 1, in which data is stored, is possible. When switching to the processing mode, the register of 10 knives also contains information on the & the address of the initial start-up of the microprogram arriving at the corresponding input of the block 7 for forming the address of micro-commands.

In the processing mode at the current time, the next microcommand enters the register 5. Its bits, corresponding to the operational part of the microcommand, are fed to the input of the decoder 8, which generates a set of signals that control the operation of blocks 7, 9, and 11. Block 9, under the influence of control signals from the decoder 8, can perform arithmetic and logical operation over one or two operands located in its internal registers or arriving at its information input through switch 6 from memory block 1. The result of the operation can be stored in internal registers, set as the address of block 1 to the input AX2 of block 1.1 or as

information for recording from its output to the 40th cycle of the generator. 18, on its switch 6. Block 9 also forms

output, the clock signals disappear, which allow the reading of the next microcommand in block 2, the reception of the microcommand in register 5 and the processing of the corresponding control signals by the decoder 8, including the input UX1 of block 11. As a result, the address from the address input of the microprocessor processor and signal

signs of the results of the operation, coming from its output to the corresponding input of the block 7 of the formation of the address of micro-commands. In block 7, under the control of signals from the decoder 8, the address of the following microcommand from the address part of register bits 5 arriving at the information input of block 7 is formed, taking into account the signs of ramification. 5 addressing the decoder 22 last

output, the clock signals disappear that allow the reading of the next microcommand in block 2, the reception of the microcommand in register 5 and the processing of the corresponding control signals by the decoder 8, including the input UX1 of block 11. As a result, the address from the address input of the microprocessor and the signal

coming from block 9. When forming the starting address, the contents of register 10 are used. Block 7 is ana. It lyzes the generated address code and generates a control signal, 55 steps to the control input of switch 4 and the control input UX1 of unit 2, allowing the microcommand to be read from it.

on one of its three outputs, it generates a signal corresponding to the resolution of access to register 1.0, block 2 or block 1. The code receiving signal in register 10 is generated by the eleg. ment 15 when there is a recording signal at the control input UX4 of block 11. The signal for accessing block 2 is produced by element 16, which is in rage

50

five

If the generated address is the address of block 3, the next micro-instruction enters register 5 from block 3 via switch 4 via one of its information inputs. If, however, a call is made to block 2, other information inputs of switch 4 are opened. The control signals of the decoder 8 received at the control input UX1 D) of lock 11 are signals for issuing the address, reading, writing, and accessing block 1 of the operative memory by microcommand. If they are available, block 11 receives from block 9 an address and sends it together with SI1 reading or writing channels via outputs AB1 and UVZ to block 1. Switch 6, which is controlled by the control inputs UHZ and UX4, connects the bi-directional information input of the block

Ik output when reading or information input when writing block 9.

In case of a conflict situation when accessing block 1 from the side of the microprogram to the inputs AX2 and UX1 of the block

I1 and from the external inputs of the microprocessor processor at the inputs of AHZ, UH4 and UHZ unit 11, the latter solves the conflict situation on the principle of servicing the first incoming request.

Consider the operation of control block 11.

The first input of the generator 18 receives a signal that determines the mode of operation of the microprocessor processor. If this signal corresponds to the loading mode, it stops at the end of the generator-work cycle. 18, on his

address to the decoder 22 last

output, the clock signals disappear, which allow the reading of the next microcommand in block 2, the reception of the microcommand in register 5 and the processing of the corresponding control signals by the decoder 8, including the input UX1 of block 11. As a result, the address from the address input of the microprocessor processor and signal

on one of its three outputs, it generates a signal corresponding to the resolution of access to register 1.0, block 2 or block 1. The code receiving signal in register 10 is generated by the eleg. ment 15 when there is a recording signal at the control input UX4 of block 11. The signal to access block 2 is generated by element 16, which in razhi51462339

e processing is blocked. The signal to block 1 is generated by trigger 17. In the loading mode, it is set to one for the first and third inputs according to the principle of operation of the 1K-trigger and due to the fact that at the second input of the SLOTPLE or 21 control signals Inlet UH1 of block 11 is absent. The single state of trigger 17 permits the switching of the address input of the microprocessor processor. a switch 12 to the address input of block 1 and control signals for reading 15 write from the third and fourth input of switch 14 to the control inputs of block 1 and switch 6. The operation end signal is generated at the output of delay element 13 through element 20, which converts the turn signals to register 10 and blocks 1 and 2, the delay value is determined by the speed of blocks 1 and 2.

When switching to the processing mode, the generator 18 at the first input starts up, at its output the clock signals appear, allowing the selection and execution of microcommands. When accessing block 1 by microcommands, register 19 receives the address at the input AX2 of block 11 from block 9 by the corresponding control signal, which arrives at the control input of register 19. The read and write signals go to the first and second inputs, switch 14 , a: signal to the second inputs of elements 21 and 23 and trigger 17. If there is no access to block 1 from the external inputs of the microprocessor processor, trigger 17 is reset, and switches 12 and 14 are connected to the address and control 20

25

thirty

35

40

X N llU ruJijv - ci. L x t (f - J -. OA

to the inputs of block 1, respectively, 45 dah element 30.

It does not remove the sig of element 21. He stumbles on the element, removes the element 23, and should work. or writing to the block If the call is not completed and the external sides of the external to the multi-processor, trigger 17 and the signal on them

Unit 2 can operate in data recording and in p commands. The first re-boot mode m processor. At this 26, the address with the firmware control action is passed to the power supply 33 for the data, also passing the cutting elements 29 and the storage drive 33 is read from the storage devices 24, stdout 24 or lower strings, 28 or 27 write times, dependent on the lower-order output com

In the mode of operation, it sends microcommands to the input, and 33 times the accumulator, an element of 30 hours, the signal is provided by the command and the tactical command

the address in register 19 and the control signals on the first and second inputs of the switch 14. If the microcommand access signal arrives at block 1 from the external inputs of the microprocessor process, the first input of the EXCLUSIVE OR 21 element is From the decoder 22. As a result, the trigger 17 is not transferred and the element 23 is triggered, which sends a signal to the second input of the generator 18. The generator 18 pauses, delaying the execution of the microcommand for a time, the switch 6 mutates in a double way.

When addressing 1 and there is a signal, from the value of the address at the input, the ae bidirectional microprogram opens with information from the second or second in par. 6. When recording from the first

0

five

0

five

40

Oa

As the signal at the first input of the element 21 is not removed. After its removal, the element 21 is triggered, the trigger 17 is reset, the signal at the output of the element 23 is removed, and the generator 18 continues to operate. There is a read or write to block 1 by microinstruction. If the call on the microcommand is not completed yet and the call comes from the external inputs of the microprocessor processor, it is delayed by the trigger 17 and element 21 until the signal at their second inputs is removed.

The main memory unit 2 (FIG. 3) can operate in the mode of reading and writing data and in the mode of reading microcommands. The first mode corresponds to the mode of loading the firmware processor. In this case, the switch 26 passes to the address input of the accumulator 33 the address from the address input of the microprocessor processor under the action of the data call control signal, which also permits the reading signal to pass through elements 29 and 32 to the input of the sample of the memory 33. When reading, the double word is read from the accumulators 24 and 25. When recording, the recording strobe of the higher 24 or junior accumulators by elements 28 or 27, if there is a recording signal, depends on the value of the lower bit of the address on the control the output of the switch 26.

In the processing mode, the switch .. 26 supplies the address of the microcommand to the input of the accumulator 33, and the input of the sample of the accumulator 33 transmits a signal from the output of the element 30 through the element 32 in the presence of a microcommand signal and a microcommand reading clock signal on the first and second inputs of the element 30.

The data switch 6 (FIG. 4) switches the double word of block 1 as follows.

When requesting data in block 1 and the presence of a read signal, depending on the value of the low-order bit of the address, element 40 or 41 opens at the input and output of element 43, and the bi-directional information input of the microprocessor processor is supplied with information respectively from the first or second inputs AND 2 of the switch 6. .When recording information is fed both to the first AND 1, and to the second

swarm AND 2 inputs of switch 6 through elements 36 and 37.

When accessing unit 1, switch 6 commutes the following

shimm way.

When accessing block 1 by microinstructions, which is determined by an inverse signal at the input of element 34, element 35, 1 opens during reading, allowing transfer to block 9, and element 39 is opened during recording. When accessing external control signals, with my signal at the input of element 34, element 1 opens in 1 reading, and element 38 in writing,

Thus, the microprogram processor provides the following functions: first, it can work on microprograms stored in the block of permanent microprogram memory, second, it can execute dynamically changeable microprograms that are in the operative memory block ti, implement the principle of dynamic microprogramming; thirdly, it can receive and transmit data and microprograms in operational blocks using external address, information and control inputs and outputs. The mentioned functionality of the microprocessor processor makes it possible to effectively use it as a coprocessor for performing specialized functions when complexing with a computer. In this case, the central computer can download data and firmware to the corresponding RAM blocks of the microprocessor processor, receive the processing results, pause the processing and change the processing algorithm, initiating or downloading new firmware.

Claims (1)

Invention Formula Firmware processor containing first and second RAM blocks, microprogram memory block, microinstruction switch, data switchboard, microinstruction address generation block, arithmetic logic unit, command register, control block and control signal decoder, first, second and third outputs which are connected respectively with five 0 5 0 5 40 45 50 55 the control input of the microcommand address forcing unit, the input of the operation code of the arithmetic logic unit and the first input of the control unit, the address input of the first RAM block is connected to the first output of the control unit, the address field output and the local control field output field are connected to the first one the information input of the micro-command address generation unit and the information input of the control signal decoder, the output of the micro-command switch is connected to the information input register the micro-commands, the first and second information inputs of the first group of the micro-commands switch are connected respectively to the low and high bits of the microprogram memory, first. the second information input of the second group of micro-switches switch is connected to the first information inputs-outputs of the second RAM and data switch, the second information input of the second group of micro-switches switch is connected to the second information inputs-outputs of the second RAM block and data switch; the microinstructor addresses are connected to the address of the address of the microprogram memory block and the first address input of the second RAM block, the identification identification output is The microcontroller of the microcommand address generation unit is connected to the control input of the microcommands switch and the read input of the second memory block, the first information output of the arithmetic logic unit is connected to the second information input of the microinstruction address generation unit, the output of the command register register is connected to the information input of the microinstruction address generation unit and the second input of the control unit, the third input of which is connected to the second information output of the arithmetic logic unit, the third info mation input-output data switch coupled to an information output of the first block vhodom- RAM memory, the data information output switch coupled to the data input of the arithmetic logic unit, characterized in that, in order to expand the application area due to the possibility of combining it with other computers, the information input / output of the microprocessor processor is connected to the information input of the command register and a quarter information input / output of the data switch, the information input of the microprogram processor is connected to the fourth input of the control unit, the first control input of the data switch and with the second address input of the second memory block, the input of the input attribute of the microprocessor processor is connected to the recording input of the second memory block The second control input of the KOMisiyTaTopa data and the fifth input of the control unit, the input of the output information of the microprocessor processor is connected to the sixth input of the control unit, the output of the end sign of the operation of the microprocessor processor is connected to the second output of the control unit, the fifth information output of the switch data is connected to the third information output of the arithmetic logic unit, the third output of the control unit is connected to first mode control input the main memory unit and the third control input of the data switch, the fourth output of the control unit is connected to the input of the command register entry, the fifth output of the control unit is connected to the fourth control input of the data switch, the sixth output of the control unit is connected to the fifth control input the data switch and the first sample input of the second RAM block, the seventh output of the control unit is connected to the strobe input of the control signal encoder, the synchronous input of the microcommand registrar and the second input ki of the second memory unit, and the control unit contains the address switch, the first, second and third elements AND, trigger, delay element, control switch signals, clock generator, address register, element EXCLUSIVE OR, element OR, decryptor address, the input of which is connected to the sixth input of the control unit, the second input of which is soy 5 0 5 0 .5 0 5 Q 5 It is connected to the start input of the generator and the first input of the first element AND, the output of which is connected to the first input of the element OR and the fifth output of the control unit, the third input of which is connected to the information input of the register. address, the output of which is connected to the first information input of the address switch, the output of which is connected to the first output of the control unit, the fourth input of which is connected to the second information input of the address switch and the information input of the address resolver, the first and second outputs of which are connected respectively to the second input of the first and first the input of the second And elements, the output of which is connected to the second input of the OR element and the fourth version of the control unit, the first digit of the first input of which is connected to the input recording the address register j the second bit of the first input of the control unit is connected to the first input of the EXCLUSIVE OR element, the first information input of the trigger and the first input of the third And element whose output is connected to the lock input of the clock generator, the output of which is connected to the seventh input of the control unit, the remaining bits The first input ports of which are connected to the first information input of the control signal switch, the output of which is connected to the third output of the control unit, the fifth input of which is connected The second input of the control signal switch, the low-order bit of this input is connected to the second input of the second element AND, the third output of the address decoder is connected to the second input of the EXCLUSIVE OR element and the second information input of the trigger, the output of which is connected to the control inputs of the address switch and control signals, the second input of the third element And, the sixth output of the control unit and the third input of the element Sh1I, the output of which is connected to the input of the delay element, the output of which is connected to the second output of the block In the control, the output of the TEMPTING OR element is connected to the trigger input. // / t  HC7 Phases. 2 physical