SU905818A1 - Microprogramme-control device - Google Patents

Description

(54) MICRO PROGRAM CONTROL DEVICE

one

The invention relates to computing, is intended to form a sequence of commands while simultaneously calculating a number of functions, and can be used in dangal processing devices.

A control device containing a memory device, a clock pulse generator, a register, decoders, logic circuits, information register P. is known.

Disadvantages of the device - low speed and limited functionality.

It is also known a control device containing an arithmetic unit, a matrix of microprograms, a command counter, a return address register, a group of elements SHIII 2.

The drawbacks of the device is the low speed and complexity of construction.

The closest in technical essence to the proposed is

a device containing a command register, a command address modifier, a micro-command address register, a memory block, a micro-command register, an additional conditional branch block, an I / O block, an interrupt block, a switch 3.

Admittedly: devices are limited functionality, since it does not allow organizing parallel execution of several programs.

The aim of the invention is to extend the functionality by organizing parallel

15 running a number of programs.

Claims (3)

The goal is achieved by the fact that the device containing the micro-register, the memory block, the micro-address address register, the address fixator, the first block of AND elements and the command register, whose input is the input of the device’s initial address, and the output of the register 39 mandrel are connected to the first information input of the address modifier, the information output of which is connected via the address register of micro-instructions to the address input of the memory block, the first information output of which is connected to the second information input of the modifier address a, the first control input of which is connected to the output of the first block of elements; And the first input of which is the input of the device transition signs, and the second information output of the memory block is connected to the information input of the microinstructions register, the processing units of the subroutines are entered, the second block of elements I, the control trigger laziness, the register number of the subprogram processing unit and the decoders, the input of the first decoder is connected to the first information output of the microinstructions register, the second information output of which is connected to the information the input of the second decoder and the information inputs of the subprogram processing units, the control inputs of which are connected to the corresponding outputs of the second decoder, the control input of which is connected to the corresponding output of the first decoder, the outputs of the ijoTopor are the output of the micro-instructions register, the third information output the input of the first block of elements And, with a single input of the control trigger, and with the information input of the register of the block number of processing subprograms, nny vyho coupled to a first input of the second block member and the output is connected to torogo zero input control trigger, the zero output of which is connected to a second control input of the address modifier. The control feature inputs of the device are connected to the inputs of the conditions of the subprogram processing units, the first control outputs of which are connected to the second input of the second block of AND elements, and the second control outputs of the subprogram processing blocks are the outputs of the control commands of the device. In addition, the subroutine processing block consists of an address modifier, a memory block, a microinstruction register and an And block whose first input is connected to input 4 of the conditions of the subprogram processing block; The first input and the first information input are connected respectively to the control and information inputs of the subprogram processing unit, the information output and the second information input of the address modifier are connected according to but with the address input and the first information output of the memory block, the second and third information outputs of which are connected respectively to the register input of microcommands and the first control output of the processing subroutine unit, the first and second discharge outputs of the register of microcommands L, respectively and with the second control output of the subprogram processing unit. Fig. 1 is a functional block diagram of a firmware control device; in fig. 2 - functional block processing subroutines. The device contains subprogram processing blocks, register of 2 commands, modifier of 3 addresses, register of 4 addresses of microinstructions, block 5 of memory, register of 6 microcommands with zones 7 of the initial address of the subroutine, microoperations 8 and conditional transition 9, first block 10 of elements And, trigger II control , first decoder 12, register 13 of the number of the processing unit of subroutines, second decoder 14, second block 15 of elements AND, input 16 of the initial address, input 17 of transition signs, outputs 18 of control commands, inputs of 19 signs of control, outputs of 20 micro-operations, modificato p address 21, memory block 22, register of micro-commands 23, block 24 of elements I. Subprogram processing block 1 contains address modifier 21, memory block 22, micro-command recorder 23, block of elements I. The input control signal 16 sets the initial address of the program device, which through register 2 is transmitted to the modifier 3, which generates the starting address and through register 4 outputs it to block 5. At a given address from block 5, micro-command is read into register 6. Zone 7 defines the initial 5. addresses of subroutines in blocks 1, and also determines the number of block 1 that needs to be started, the number goes to decoder 12, the control signal for which is one of the microoperations of outputs 20 coming from decoder 12 and determined by bits of zone 8 of the register 6. The outputs of the decoder I2 are start-up lines for blocks J. Zone 9 of register 6 defines in block 10 the number of the transition flag, by which it is necessary to make a conditional transition to another program. If the corresponding transition flag is executed, then from block 10 a signal is issued to the modifier 3, in which the address change occurs, but if the sign is not executed, then the following address is determined by the address part of the bits of block 5 entering the second input of the modifier 3. Zone 9 if necessary, it can put the firmware in control into the standby mode, while in register 13 the block number is set to 1, a stop signal is sent to the trigger 11, which blocks the modifier 3. Block 15 passes the selected Ready signal from block 1 corresponding corresponding to the number in register 1 and sets the trigger 11 to the state O, unlocking the modifier 3. The device operates as follows. At the address recorded in register 4, from block 5, the content of this address is selected, consisting of the address and operating part. The address to the part from the output of block 5 enters the input of modifier 3 and sets the code for determining the next program address, the operational part from the output of block 5 goes to register 6. Zone 8 is decrypted in decoder 12, and at its outputs 20 micro-operation program. The code from zone 9 arrives at block 10 if a conditional transition (program branching) is required by the program. In this case, block 1 from zone 9 receives the code of the number of the transfer prize and the bit indicating the conditional transition. If the sign of the specified number satisfies the transition condition, then the signal from the output of block 10 is sent to the modifier, where a change in 86 of the address part coming from block 5 occurs. In this way a program is branched out. If the transition condition is not met, then the address is determined by the address part of the bits in block 5 (the next program). If one of the microoperations from the output of the decoder 12 indicates the start of the subroutine of a block 1, then in zone 7 of register 6 it is indicated the Hcwep of this block I arriving at the decoder 14, and the starting address of the necessary subroutine of this block 1 arriving at its input. A micro start operation from the decoder I2 passes through the decoder 14 and starts the corresponding block I. Then the next block 1 is started, and so on. according to the program of calculations recorded in block 5. All blocks can work simultaneously on their own subroutines, performed each specific task. Each block 1 at start removes its Ready signal from the input of block 15, and at the end of the subroutine restores it. Each block 1 has the necessary control feature outputs 19 for branching out its subprograms and issues the control commands necessary for a specific task to the outputs 18. The main program of block 5 can work continuously and simultaneously with blocks 1, sending information between the nodes subordinate to block I, and others operations, generating commands that are not part of blocks 1, and can also work in standby mode for operation or end of operation of blocks 1. In this case, the bits of zone 9 of register 6 are transferred to register 13, sec Call the block number that you want to query for readiness for work. One of the bits of zone 9 sets the trigger 1 1 to state 1, and the main program of block 5 stops. The code of the block number I of register 13 goes to block 15, the Ready bus of the indicated block 1 to trigger 11. When the Ready signal appears, trigger I1 is set to the state O and the program of block 5 is restarted. Thus, the proposed device makes it possible to organize the parallel operation of various controlled nodes when calculating several functions simultaneously, i.e. allows to expand the functional capabilities of the known device due to the organization of parallel programming. 1. Microprogrammed control device containing microinstructions register, memory block, microinstructor address register, address modifier, first block of AND elements and instruction register, whose input is the input of the device’s initial address, and output of the register of commands to the first information input address modifier, whose information output is connected to the address input of the memory unit through the micro-command address register, the first information output of which is connected to the second information input modifier and the address, the first control input of which is connected to the output of the first block of elements AND, the first input of which is the input of the device transition signs and the second information output of the memory block is connected to the information input of the register of microinstructions, in order to expand the functional capabilities capabilities due to the organization of parallel execution of a number of programs, 3 subprogram processing blocks, the second block of K elements, the control trigger, the register number of the subprogram processing block and decoders, the input the first decoder is connected to the first information output of the register of micro-instructions, the second information output of which is connected to the information input of the second decoder and to the information inputs of the processing units of the subroutines whose control inputs are connected to the corresponding outputs of the second decoder, the control input of which is connected to the corresponding output of the first decoder, the outputs of which are tricks of the device’s micro-operations, the third information (the live output of the register of micro-commands 88 is connected to the second One of the first block of I elements, with a single control trigger input and with the information input of the register number of the subprogram processing unit, whose information is connected to the first input of the second block of I elements, whose output is connected to the zero input of the control trigger, the zero output of which is connected to the second control input address modifier, device control feature inputs Connected to the inputs of the condition of subprogram processing blocks, the first control outputs of which are connected to the second input of the second unit Each of the AND elements and the second control outputs of the subprogram processing units are the outputs of the device control commands. 2. The device according to claim 1, characterized in that the subprogram processing unit consists of an address modifier, a gamma block, a microinstructions register, and an I block, the first input of which is connected to the input of subprogram processing unit conditions, the output of the I block of elements, control module input of the address modifier, the second control input and the first information input of which are connected respectively to the control and information inputs of the subprogram processing unit, the information output and the second information input modifier and the addresses are connected respectively to the address input and the first information output of the memory block, the second and third information outputs of which are connected respectively to the register input of micro-instructions and the first control output of the processing block of subroutines, the first and second bits of the register of micro-instructions are connected respectively to the second input of the block And. And with the second control output of the processing unit of subroutines. Sources of information taken into account during the examination 1. USSR author's certificate No. 291201, cl. G 06 F 9/16, 1969. 2. USSR author's certificate number 596947, cl. G 06 F 9/16, 1976. 3. Electronic industry, 1978, № 6, p. 49-54 (prototype).