SU1115054A1 - Firmware control unit - Google Patents

Abstract

MICROPROGRAMME CONTROL DEVICE containing a microinstructions memory block, command register, microinstructions register, address counter, address generator, logical conditions decoder, clock generator, trigger, first block of AND elements, block of OR elements, first OR element, delay element, and input The device command code is the information input of the command register, the input of the logical conditions code of the device is the first input of the first block of AND elements, the second input of which is connected to the output of the decoder logical These conditions, the input of which is connected to the first input of the block of the OR elements and the output of the logic code of the microcommand register, the output of the operation code of which is the control output of the device, the second input of the block of the OR elements, is connected to the output of the first OR element, whose input is connected to the output of the first block of elements AND, the output of the block of elements OR is connected to the information input of the address counter, whose information output is connected through the address decoder to the address input of the microcommand memory block, the output of the end mic The microcommand register rookomand is connected to the summing address input, the device start input is the input of setting 1 trigger, the output of which is connected to the input of the generator start (L ra clock pulses, the output of which is connected to the address decoder gate input and through the delay element with the synchronization input res A micro-command microgroup, characterized in that, in order to reduce the volume of the equipment, it contains a buffer register, modulo two, the second and third blocks of AND elements, the second OR element, the SP element NOT, one ovibrator element and on And, the first register of commands vpsod connected s.pervym second input; And the first input of the second element SH, the second input of which is connected to the second output of the command register and to the first input of the third block of elements AND, the second input of which is connected to the second input of the second block of elements And to the output of the one-shot whose input is connected with the output of the second element OR n through the element NOT - with the first input of the element I, the second input of which

Description

the microinstructions register command is connected to the end output; the information input of the kotoropo is connected to the modulo two adder output, the first and second inputs of which are connected respectively to the output of the microcommand memory block and to the output of the buffer

A register whose information input is connected to the output of the second AND block of elements, And the output of the third block of elements AND is connected to the third input of the block of OR elements, the output of the AND element is connected to the input of the installation in O of the trigger.

The invention relates to computing and can be used in the construction of devices and computer control systems, automated process control systems, controllers.

It is known a firmware device — a control, in which the storage of the firmware of the operations is performed in a memory device with a sample of them depending on the operation code and the order that occurs during the execution of LIJ operations.

The drawback of the device is the redundancy of the firmware memory block.

A firmware control device is known that contains an address register, an address decoder, a micro-register register drive, the accumulator inputs are connected to the address decoder outputs, and the outputs are connected to micro-register register inputs, the address outputs of which are connected to the first address register input, the second input of which is a device input ,, the output of the register of the address is connected to the input of the address decoder 21.

The disadvantage of such a device is that a storage device is used for storing micro-commands, the capacity of which depends on the number of micro-commands and the number of micro-operations in a micro-command.

A firmware control device is known that contains two memory blocks, AND element blocks, an address register, decoders, a micro-command counter, a micro-register register, a clock pulse generator, an AND, OR, NOT, delay elements.

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The disadvantages of this device is the low efficiency of the storage block of operating schomes and a narrow scope, which necessitates the increase of the storage block when expanding the list of operating micro-commands.

A microprocessor control device is known that contains an arithmetic unit, a micro-operation matrix, a microprogram matrix, a command counter, a control transfer address register, a decoder, a return address register, a group of AND elements and a group of OR elements 41.

The disadvantage of this control device is the impossibility of executing commands that do not enter the main set of computer commands.

It is also known a firmware control device containing the command register, the microinstructor address driver, the microinstructions register, the permanent memory block, the address register, the address switch, the address decoder, and the RAM block 15. The disadvantage of the device is that the user needs to modify or supplement the contents of the RAM.

The closest in technical essence and the achieved positive effect to the invention is a microprogram control device containing a command register, a microinstruction address modifier, microinstruction address registries, a decoder, microinstructor addresses, a memory block, a register microinstruction, a command decoder and a trigger, and the command input the command register is the device's command input, the output of the command register is connected to the first input of the microinstruction address modifier, the output

which is connected to the information input of the micro-command address register, the output of which is connected to the second input of the micro-command address modifier and to the input of the micro-command address decoder, the output of which is connected to the memory block input, the output of which is connected to the micro-command register information input, the control output of which is the device’s output, and the address output of the micro-register register is connected to the third input of the micro-address address modifier, the fourth input of which is the input of the device conditions, the output a trigger coupled to a fifth input of modifier microinstruction address, and the count input of the flip-flop - Sodin yield decoder command input coupled to a command input device used.

A disadvantage of the known device is the inability to expand the main command list without increasing the size of the micro command memory block.

The chain of the invention is to reduce hardware costs by expanding the set of microinstructions without increasing the size of the memory block,

The goal is achieved by the fact that a microprogram control device containing a microinstructor memory block, a command register, an address counter, an address generator, a logic condition decoder, a clock pulse generator, a trigger, the first block of elements AND, a block of elements ШШ, the first element OR, element delays, the input of the command code of the device being the information input of the command register, the input of the code of the logical conditions of the device — the first input of the first block of elements AND, the second input of which is connected to the output of the decoder; conditions, the input of which is connected to the first input of the EW unit and the output of the logic code register of the microcommands, the output of the opcode of which is the control output of the device, the second input of the OR element block, which is connected to the output of the first the block of elements I, the output of the block of elements SHS - with the information input of the address counter, whose information output is connected

through the decoder with the address of the microinstructions memory block, the output of the microcommand end of the microcommand register with the summing input of the address counter of the device start input is the input of setting 1 trigger, the output of which is connected to the trigger input of the clock generator, the output of which is connected to the gate of the address decoder and through delay element - with the micro-command register synchronization input; a buffer register, modulo two, the second and third blocks of AND elements, the second OR element, the NOT element, and one the driver and the AND element, the first output of the command register is connected to the first input of the second block of AND elements and to the first input of the second OR element, the second input of which is connected to the second output of the command register and to the first input of the third block of AND elements, the second input of which is connected to the second input of the second block of elements And with the output of the one-shot, the input of which is connected to the output of the second element OR, and through the element NOT to the first input of the element AND, the second exit of which is connected to the output of the end of the microinstruction register command, infor The mapping input of which is connected to the output of an adder modulo two, the first and second inputs of which are connected respectively to the output of the microinstructions memory block and to the output of the buffer register, whose information input is connected to the output of the second block of elements I, the input of the third block of elements I to the third input the block of elements SHS, the output of the element I - with the input of the installation in О of the trigger.

The essence of the invention consists in modifying a micro-command by imposing on it a mask code and thereby changing the code of the micro-command issued to the control. The mask code is set by the user, which allows him to expand the main set of control commands,

The introduction of the buffer register allows you to store the mask code from the first information flow of the device through the command register and the second block of AND elements,

The introduction of a modulo-two adder allows modification of a micro-command selected from the memory block by overlaying some mask code on it. Due to this, changing the code in the buffer register will use microcommands from the memory block for new applications. The introduction of the second element of the IL, the one-shot and the relations due to them, makes it possible to rewrite the information during the transition to the execution of the next command. The introduction of the second block of the And elements and the conditional links it needs is to define the next sequence of microcommands after the previous one. The introduction of the element HE and the element AND, as well as the relationships due to them, to reset the device after the firmware has been executed. The drawing shows a functional diagram of the proposed device. The microprogram control unit contains a block of 1 memory of micro-commands, a register of 2 commands with zones: 2.1 - zone of expansion of the set of operations; 2.2 - zone of operation code, buffer register 3, register of 4 micro-commands with zones: 4.1 - zone of micro-operations; 4.2- code zone of logical conditions; 4.3-zone signal end microcommand; 4.4 - signal zone command end, address counter 5, address decoder 6, logic decoder 7, modulo 8 adder two, 9 clock pulses, trigger 10 first 11, second 12 and third 13 block and elements AND 14 elements OR one-shot 15, first 16 and second 17 elements and OR, element 18, NOT element 19, delay element 20, command code input 21, logic condition code input 22, start input 23 and control output 24. The microprogram control device works as follows . In the initial state, the memory elements of the device are in zero state. The device operates in two modes: when sending a regular command list, the firmware of which is recorded in the microinstructions memory block, and when implementing an extended command list, when enlarging the command list requires firmware expansion. 54 The operation of the device when implementing the usual list of commands. In the initial state, the memory elements of the device are in the zero state. The command code entry 21 enters the register 2 teams. When the device operates in the mode of implementing the usual list of commands (specified by the set of microprograms stored in memory block I), the value of the bits in zone 2.1 of register 2 is zero. At the information output of zone 2.2 of register 2, the command sets the code of the operation to be performed. When a code appears in zone 2.2 of register 2, it will be shown via the OR element. 17 an impulse appears at the output of the single-vibrator 15. This impulse permits the rewriting of information through the second 12 and third 13 blocks of the AND elements from the register of 2 commands, respectively, to the buffer register -3 and to the counter 5 of the address. In the address counter 5, a code is written defining the starting address of the first microcommand of the firmware. The device starts operation when a pulse is received from input 23. This pulse throws the trigger 10 into one state. After setting the trigger 10, the 9-clock pulse generator starts generating pulses. First: a clock pulse from the output of the generator 9 enters the gate input of the address decoder 6 and samples information from memory block I to the address recorded in the address counter 5. Since the buffer register 3 in this mode of operation is in the zero state, after selecting information from memory block 1, the information through the modulo two modulator is entered into the register of 4 microcommands. After retrieving information about the first micro-command from memory block I and writing it to the micro-command register 4, a clock pulse through delay element 20 arrives at the micro-command register register 4 and issues the operating part of the micro-command from zone 4.1 of the register 4 to the control output 24 for control, for example , an arithmetic unit of the processor. Simultaneously with the issuance of the operating part of a microcommand from zone 4.4 of register 4, a label is issued - a sign of the issuance of a microcommand. This label enters the counting input of the counter 5 address and increases its contents by one. The next clock pulse from the output of the generator 9 reads information from the memory block into the register of 4 micro-instructions and provides control. Similarly, the issuance of a linear sequence of microinstructions

In the case of the microcommand of the branching, the operational lacTb microcommand enters the register of 4 microcommands (the code is entered into zone 4.1) and the code of the logical condition being checked (the code is entered into zone 4.2). When issuing information (branching microcommands) from the register of 4 microcommands, the code of the logical condition being checked containing the fixed part and the modified bit goes through the block 14 of the elements OR to the counter 5 of the address and simultaneously to the decoder 7 of the logical conditions. The information about the checked logical condition from the input 22 of the device enters the input of the block 11 of the elements AND, and, if the checked logical condition is fulfilled, the output of the element OR 16 is a signal of a logical unit that changes the values of the modified address bit in the counter 5 of the address , the initial address of the microcommand of the next linear sequence is finally formed, and the operation of the device will continue similarly to that considered.

When issuing the last microcommand of the microprogram in the zone 4.3 of the register of the 4 microcommands, a label is issued - a prikazak as the end of the microprogram. This label goes to the input of the element And 18. In the event that in the register of the 2 commands there is no information on the performance of the next firmware, then

the element OR 17 and the element NOT 19 are given permission to reset the trigger 10 by a label - a sign of the end of the firmware.

The operation of the device when implementing an extended list of commands.

The operation of the firmware control device when implementing the extended command list is similar to the operation of the device when implementing the usual command list. A distinctive feature is that if it is necessary to implement an additional command, the firmware of which is absent in the memory block, some code is entered into the zone 2.1 of the register 2 of the commands.

When a code appears in zones 2.1 and 2.2 of register 2, a pulse appears at the output of the one-shot 15, which overwrites information from register 2 to buffer register 5 and counter 5 of the address. The calculated first linear linear microinstruction from memory block 1 is fed to the adder 8 modulo two where it is modified by the code received from buffer register 3. The modified microcommand from modulator 8 modulo two is entered into the register of 4 microcommands and is output to the clock input of the pulse. devices. Further, the device functions similarly to the one considered.

Thus, as a result of modifying the micro-instructions recorded in the memory block, a new additional command (or list of commands) is implemented without expanding the control memory.

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Claims (1)

A MICROPROGRAM CONTROL DEVICE comprising a micro-memory block, a command register, a micro-register, an address counter, an address generator, a logical condition decoder, a clock generator, a trigger, a first AND block, an OR block, a first OR element, a delay element, and a code input device commands is an information input of the command register, the input of the logical conditions code of the device is the first input of the first block of AND elements, the second input of which is connected to the output of the decoder of logical conditions input, the input of which is connected to the first input of the block of OR elements and the output of the code of logical conditions of the register of microcommands, the output of the code of operations of which is the control output of the device, the second input of the block of elements OR is connected to the output of the first OR element, the input of which is connected to the output of the first block of AND elements , the output of the OR block of elements is connected to the information input of the address counter, the information output of which is connected through the address decoder to the address input of the micro-command memory block, the output of the micro-command end is register and the micro-command is connected to the summing input of the address counter, the start-up input of the device is the setup input of 1 trigger, the output of which is connected to the input. the start of the clock generator, the output of which is connected to the gate input of the address decoder and through the delay element with the synchronization input of the micro-register register, characterized in that, in order to reduce the amount of equipment, it contains a buffer register, an adder modulo two, the second and third blocks of AND elements, the second OR element, the NOT element, the one-shot and the And element, p When in use, first output instruction register connected to an input of second s.pervym; . of the first block of AND elements with the first input of the second OR element, the second input of which is connected to the second output of the command register and the first input of the third block of AND elements, the second input of which is connected to the second input of the second block of AND elements and with the output of the one-shot, the input of which is connected to the output of the second OR element and through the element NOT - with the first input of the AND element, the second input of which is connected to the output of the end of the micro-register register command, the information input of which is connected to the output of the adder modulo two, the first and second inputs to of which are connected respectively to the output of the micro-command memory block and to the output of the buffer register, the information input of which is connected to the btopqto output of the AND block, the output of the third block of AND elements is connected to the third input of the OR block, the output of the AND element is connected to the trigger input of 0.