SU1410039A1 - Storage addressing device - Google Patents

Abstract

The invention relates to computing and can be used in the construction of microcomputer memory systems. The purpose of the invention is the expansion of the functional capabilities of the memory addressing device due to the realization of the possibility of addressing additional memory equal to the main volume. The goal is achieved by introducing the elements And 7 10, 11, 13, 14, elements HJM 8 and 15, triggers 9 and 12 into the device. These elements form an additional address bit depending on the state of the address byte address of the computer trunk and on command type (byte-byte). When developing programs for a computer system with a memory addressing device, standard programming automation tools can be used, 1 Il. SS

Description

with X)

The invention relates to computing technology and can be used in the construction of memory systems; microcomputers.

A: The purpose of the invention is to expand the functionality of the device; STV by re-enacting the possibility of addressing additional GTA: "equal to the main volume,

The drawing shows the functional diagram of the device ,,

The memory addressing device contains a register of 1 commands, an arithmetic logic unit 2, a decoder of 3 commands a block of 4 address control of a microcommand, a block 5 of a control memory, a register of 6 microcommands, an AND 7 ,, element / an OR 8 element, the first trigger 9, elements And 10 and 11, the second trigger 12 ,, elements And 13 and 14, the element OR 15 and has information input 16, output 17 of the address of the next command, output 18 of the additional address bit

The device works as follows.

A command selected from the memory through input 16 enters the command register 1 and is written into it in the micro program. From the command register 1, commands are sent both to the arithmetic logic unit 25 and to the input of the decoder 3 commands. of the command code, the microcontroller jpecoM ad control unit 4 generates a ngmal address of the microprogram execution of the given command. At the generated microcommand address, from the control memory block 5, a microcomand is selected, which is then written to the 6th register of the microscopic register. In the register arithmetic logic unit 2, one of the registers is used as counters

The sign of the byte record will be in the zero state. Thus, at the time of going to the SHSh 15 element there will be a byte addressing (OOp) bit state and therefore in the additional nf-1 bit of the trunk there will be a zero state if the command and data address is even and the unit state, ec.im- the address of the command or data is odd. When executing commands with byte operations, the call for operandglc is made to the memory from which the command is selected, since in this case the output of the decoder of the 3 commands will contain a byte sign, and therefore the trigger 9 of the byte record will be set to normal, so how the output of the element And 7 is formed impulse o. At the output of the element And 13 will be a log about 1 or a at the output of the element And 14 log. O, while at the output of the element 1-SHI 15 and at the output 18 of the device there will be a state depending on the command increase

Ф о рм ул and

and

gaining

A memory scheduling device, a co-ordinated command register, an arithmetic log. Unit, command commands, a microcommand address control block, a control memory block, a microcommand register, the command register information input being the information input of the device, the register entry input commands are connected to the inputs of the arithmetic logic unit, the microcommand address control block, and B, 1 input of the microcode register microprogram, the output of the command register is connected to the information input of the decoder Andes and data input arithmetic-lo

addresses of commands to which on the microprogram unit, whose bit outputs are the device's address outputs, the start address output. the command decoder is connected to the information input of the microcommand address control unit, the resolution output of which is connected to the command decoder resolution input, the output of the microprogram's start address of the microcommand address control module is connected to the address input of the control unit block, the control cone memory unit output , is included with the information input of the register of microcommands., distinguished by the fact that, for the purpose of the extension program, the address of the next command that will be present at the output 17,

Element And 11 selects at the microcommand address the time when the formation of the address of the command begins. The pulse generated at the output of the And 11 element sets the trigger 12 of the command address feature to zero or one state depending on the state of the byte address address bit (OOr of the trunk), and if the command is not a byte, then the output of the And 13 will be the zero state ,, since trigger 9

0

five

Secondly, the device’s address outputs, the start address output. the command decoder is connected to the information input of the microcommand address control unit, the resolution output of which is connected to the command decoder resolution input, the output of the microprogram's start address of the microcommand address control module is connected to the address input of the control unit block, the control cone memory unit output , is equipped with an informational input of the register of microcommands., distinguished by the fact that, in order to expand the class of solved tasks by addressing the additional memory equal to the main volume, in it There are five elements And, two elements, OR, two, and the inputs of the first element And are connected to the corresponding output bits of the initial microprogram address of the microcommand address control block, the output of the first element And is connected to the synchronization input of the first trigger, the reset input of which is connected to the reset output of the microcommand address control unit and with the first input of the first OR element, the second input of which is connected to the output of the second AND element, whose inputs are connected to the corresponding bits of the information output of the the microinstructions gistra, the first input of the third element I is connected to the output of a command byte instruction of the command decoder, the resolution input of which is connected to the second input of the third element AND whose output is connected to the installation input of the second trigger, the reset input of which is connected to the output of the first element OR, my exit is second trigger. connected to the first input of the fourth element I, the second input of which is connected to the output of the first trigger, whose information input is connected to the corresponding output of the next address of the arithmetic logic unit and to the first input of the second element OR, the second input of which is connected to the output of the fourth element AND, the inverse output of the second trigger is connected to the second input of the fifth element AND, the output of the second element OR is the output of the additional bit of the address of the device.

Claims (1)

Claim A memory addressing device comprising a command register, an arithmetic unit, an instruction decoder, a micro-command address control unit, a control memory unit, a micro-command register, the command register information input being the device information input, the command register writing input connected to the entries of the arithmetic-logical unit, block controlling the address of the microcommand and with the output of the microcode register micro-command flag, the output of the command register is connected to the information input of the command decoder and ormatsionnym input arithmetic logic unit, the outputs of which are addressable bits output device, output starting address. the command decoder is connected to the information input of the micro-command address control unit, the resolution output of which is connected to the resolution input of the command decoder, the output of the initial address of the micro-program address of the micro-command address control unit is connected to the address input of the control memory unit, the output of the control memory unit is connected to the information input of the micro-command register, which differs e with the fact that, in order to expand the class of problems to be solved by addressing additional memory equal to the main volume, five e AND elements, two elements, OR, two flip-flops, the inputs of the first element And connected to the corresponding bits of the output of the starting address of the firmware of the microaddress control unit, the output of the first element And connected to the synchronization input of the first trigger, the reset input of which is connected to the reset output of the address control unit microcommands and with the first input of the first OR element, the second input of which is connected to the output of the second AND element, whose inputs are connected to the corresponding bits of the information output register microcommands, the first input of the third element AND is connected to the output of the byte command attribute of the command decoder, the enable input of which is connected to the second input of the third element AND, the output of which is connected to the installation input of the second trigger, the reset input of which is connected to the output of the first OR element, direct the output of the second trigger is connected to the first input of the fourth element And, the second input of which is connected to the output of the first trigger, the information input of which is connected to the corresponding bit of the output of the next address of the arithm Tyco-logic unit and a first input of a second OR gate, a second input coupled to an output of the fourth AND gate, the second flip-flop inverse output is connected to the second input of the fifth AND gate, the output of the second OR gate is the output of an additional discharge device address.