SU1293730A1 - Microprogram control device - Google Patents

Abstract

The invention relates to computing and can be used in high-performance computing systems. The aim of the invention is to increase speed. The device contains a block of 1 constant memory, block 2 of RAM, register 3 micro-instructions two counters 4, 5 addresses, decoder 6, three multiplexers 7-9, adder 10, trigger 11, five elements And 12-16, two elements OR 17, 18-, IS-NE 19. The goal is achieved by increasing the speed of writing the required microcommands to the RAM. 3 il. FIG. 2

Description

1 12937

The invention relates to computing, can be used in high-performance computing systems and most; it is effective in systems with automatically tunable, dynamic architecture.

The purpose of the invention is to increase speed.

Figure 1 shows the functional-III on the scheme of the firmware control device; FIG. 2 is a timing diagram of clock signals arriving at the synchronous inputs of the blocks of the device, implemented, for example, on 55 elements of the 500 series; on figl and $ - the algorithm of the proposed device.

The device contains a block of 1 permanent memory, a block of 2 operational memory, a register of 3 micro-instructions, counters 4 and 5 of the address-, a decoder 6, multiplexers 7-9 of the relative address, the code of micro-commands and the transition address, the adder 10, the trigger 11 , elements AND 12-16, elements OR 17 and 18, element AND-NOT 19, input 20 of the device transition address ,. the first 21 and second 22 inputs of the load of microinstructions of the device, the input 23 of the logical condition 30 of the end of the device loading, the output 24 of the device, as well as the first 25, second 26J third 27 and fourth 28 inputs of the clock pulses of the device. In figure 2 it is indicated: T is the time of the device operation d-j, 29-32 are the clock signals arriving respectively at the inputs 25-28 of the device.

The device is designed to work with a typical set of micro-commands. 40 Suppose, for example, a microinstruction contains 20 bits, which are numbered from zero to 19th, starting from the youngest. The older 2 bits, the 19th and 18th, define the format of microinstructions, and the 00 code contained in these bits defines the first format, code 01 the second format, code 10 the third format, 11 is the fourth format. Suppose that the first format corresponds to arithmetic, the second to logical operations, the third to transitions S to the fourth to transfer operations, which include operations like loading into counter 4, 55, and recording microcommand into RAM at the appropriate address. Suppose that in the third format, the bits of the scrkomands are distributed after the next. 2 in the following way: (10-0) - address (A); 11 - memory sign (1 - microprogram memory, O - constant microprogram memory); 12 - sign, modification (1 - from the computer operating device); 13 - type of transition, relative or absolute; 14 - pointer (sign) of the transition (17-15) - type of transition; (19-18) - micro-command format, and in the fourth format: (10-0) - address (A); 11 - memory sign of ty-; 12 - modification sign} 13 - is not used; 14 - sign of the counter load 4 addresses; 15 - sign of recording in the memory block 2; (17–16), together with bit 15, form a transition type code; (19-18) - microcommand format.

The first register output 3 microinstructions connected to the first information input of multiplexer 7 corresponds to the (11-0) th bits of the microcommands for the third and fourth formats, the second output connected to the control inputs of multiplexers 7 and 8 corresponds to the 12th digit microcommands and determines for multiplexer 7 the choice of an address with memory sign from the register 3 microinstructions or from the input 20 of the device, and for multiplexer 8, the choice of a microcommand either from the main memory or from a computer processing device; the third output connected to the control input of multiplexer 9 corresponds to the 13th position of the microcommand; the fourth output, connected to the first inputs of the And 13 and 15 elements, corresponds to the 14th position of the microcommand; the fifth you “- the course connected to the first, inputs - elements AND 14 and AND-19, corresponds to the 15th micro-command section; the sixth output connected to the input of the decoder corresponds to (19-18) bits of the microcommand .. The first output of multiplexer 7, corresponding to (10-0) -th bits of the microcommand, is connected to the second information inputs of multiplexer 9 and adder 10; The second output, corresponding to the 11th bit of the micro-command, is connected to the information input of the trigger 11 and determines the operation of either the permanent or the working memory of the microprograms.

Let the first counter 4 addresses contain 11 (10-0) bits, the second

the address counter 5 is 8 (7-0) bits, then the bits (11-8) of the counter 4 and the bits (7-0) of the counter 5 connected to the first information input of the adder 10 are respectively the oldest and the youngest parts of the information word for adder 10; The (7-0) th bits (low) of the outputs of the adder 10 and multiplexer 9 correspond to the (7-0) th bits of counters 4 10 and 5, therefore the outputs of the (7-0) th bits of multiplexer 9 are connected simultaneously to counters 5 and 4, and (10-8) th bits of multiplexer 9 - only to counter 4.

The second output of the diffuser 6 is connected to the second input of the element 13 AND and corresponds to the 3rd format of the microinstruction. The first output of the decoder 6 is connected to the third input of the element 14 20 And and the second inputs of the elements AND 15 AND-NOT 19 and corresponds to the fourth format microcommand.

The transition flag for transition commands contained in a constant 25 mi 1 is always 1, and for memory commands it can, by modifying the command

grams in memory 2 and unit 1 1 st bit.

Counters 5 and 4 implement the following modes of operation, depending on the values of the control signals S1, S2 and clock signal C:

- storage: S 1 S 2 O, C 1 (0) -record:, -the direct score :, (only the storage mode is performed at C O, regardless of the values of the signals S1 and S2 at the inputs.

The outputs of the elements AND 13 and OR 17 are connected with the inputs S 1, respectively, of the counters 5 and 4, the inputs S 2 of which are not involved, which corresponds to the action of a single signal on these inputs.

The storage mode of counter 5 is used during the census into the operational memory 2 of the array of micro-instructions, and the recording of each next micro-command occurs in each subsequent cycle of the device operation.

Periodic loading of firmware into memory 2 is a normal mode of operation of the device, especially natural for a computer with a dynamic architecture. Therefore, the program is 1 and O,

For the commands of the first, second, and fourth load memory 2, to provide the maximum formats contained in one of the maximum load rates of the allocation memory 2, the instruction bit 11 (the memory type indicator) is 1, in constant of this memory - O. For the third format commands contained in RAM 2, bit 11

35

has the meaning

rt II

during the transitions within the given memory and O - during the transitions to the block 1 of the permanent memory. For the commands of the third format, contained in block 1 of permanent memory, bit 11 has a value of 0 for transitions within block 1 and l for

transitions to block 2 of the RAM.

40

45

Constant memory 1.

During the loading of memory 2 before the end of the array census, in each subsequent cycle from memory 1 to register 3, the same census command is selected at the same address, while counter 5 is transferred to the storage mode, which is provided by its synchronous input zero signal. In general, the signal C5 on the synchronous input of the counter 5 is determined from the formula:

C5 C4 & (PFA V nFv MI), where C4 is the clock signal input to the device 28; PF4 is the sign of the fourth microcommand format (corresponds to the first output of the decoder 6), PZ is the sign of writing to memory 2

Bit 11 of device input 20 repeats the value of bit 11 of the command selected for register 3, except for commands of the third format. For example, if a command from memory 1 to another area of the same memory (11th bit is equal to O), which turned out to be defective, which was detected, for example, by diagnostics, the diagnostic program initiates a census in The memory 2 copies of the defective program and at the input 20 of the device forms the code of the initial address of the program in memory 2 and the unit 1 1-th bit.

Counters 5 and 4 implement the following modes of operation, depending on the values of the control signals S1, S2 and clock signal C:

- storage: S 1 S 2 O, C 1 (0) -record:, -the direct score :, (only the storage mode is performed at C O, regardless of the values of the signals S1 and S2 at the inputs.

The outputs of the elements AND 13 and OR 17 are connected with the inputs S 1, respectively, of the counters 5 and 4, the inputs S 2 of which are not involved, which corresponds to the action of a single signal on these inputs.

The storage mode of counter 5 is used during the census into the operational memory 2 of the array of micro-instructions, and the recording of each next micro-command occurs in each subsequent cycle of the device operation.

Periodic loading of firmware into memory 2 is a normal mode of operation of the device, especially natural for a computer with a dynamic architecture. Therefore, the memory loading program 2 to ensure maximum loading speed

Constant memory 1.

During the loading of memory 2 before the end of the array census, in each subsequent cycle from memory 1 to register 3, the same census command is selected at the same address, while counter 5 is transferred to the storage mode, which is provided by its synchronous input zero signal. In general, the signal C5 on the synchronous input of the counter 5 is determined from the formula:

C5 C4 & (PFA V nFv MI), where C4 is the clock signal input to the device 28; PF4 is the sign of the fourth microcommand format (corresponds to the first output of the decoder 6), PZ is the sign of writing to memory 2

for a command of the fourth format;

PM - a sign of the end of the array (transition condition, arriving at the input 23 of the device)

Thus, the sync signal on the synchronous input of the counter 5 is not received

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51293730

(zero value of the signal C5) only in the recording mode of the array shkando into the operational memory 2.

The device works in the following way (Fig. For, 6).

For loading to the operational memory 2 of the next microprogram, control is transferred to the loading program, for which the transfer command is executed, which is fed to the register 3 of the microinstructions either from the permanent memory unit 1 or from the operational memory unit 2. At that, the address counter 5 goes into the mode of receiving information in accordance with the control signal coming from the circuit including the decoder 6 and the AND element 13, the second 5 records the address of the first microcommand of the load program via multiplexer 7, the adder

10 and multiplexer 9, and the trigger

11through multiplexer 7, the indication of operation with block 1 of memory is indicated.

From block 1 of permanent memory to register 3 of micro-instructions, the address of the first micro-command is loaded into counter 5, the microcom by which the address of the first microcommand is loaded into counter 4, which should be written into block 2 of RAM. At the same time, a single signal from the circuit including the decoder 6, the element 15 and the element OR 17, which receives the address formed by the adder 10 and the multiplexer 9, is sent to the register 4 is fed to the control input of the address counter 4. with a zero signal, formed in a circuit including a decoder 6 and an element 13.

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40

first command loaded. grams. At the same time, on the trigger multiplexer 7 of the address of the record or from register 3 microco from information input 20 is a sign of working with block 2 of the memory, counter 4 is the reception mode information, and the address of the first meter is loaded

In the next cycle, from block 1 of the permanent memory to register 3 of microscopes to be executed, the mand selects the write command first

microcommands in block 2 of RAM. At the same time, the microinstruction arrives at the information input of the unit 2 through the multiplexer 8 either from the main memory or from the computer operating device, depending on the signal value at the second register output 3 microcommands. At the first input of the element 15 from the fourth output of the register of micro-instructions, a zero signal is received, which through the element 15 and the element ROM 17 enters the control input of the first counter 4 addresses and

ditches it in counting mode; in this case, by clock signal: gu C4 (from device input 28) the contents of counter 4 are incremented by +1 - the actual address of the first loaded word is obtained into RAM 2. Therefore, when counter 4 is loaded, it should be sent address constant, which is one less than the actual starting address of the array being loaded. Counter 5 remains in the storage mode (the address is not modified), since its synchronous input receives zero

signal. Then, the microcommand is recorded in the operational memory 2 according to the signal coming from the output of the element OR 17 when single signals at its inputs coincide with the output

decoder 6, p of the output (sign of writing in memory 2) of register 3 and the clock input 26 of the device.

five

0

At the beginning of the cycle of recording the last microcommand in memory 2 on. At the device input 23, a single signal of the condition appears, which through the element OR, 18 and AND 16, when coinciding with the clock signal from the device input 28, enters the synchronous input of the counter 5, according to which the contents of the counter 5 is increased by +1 and the register 3 from the block 1 fixed memory, the next command is called, for example, the command to transfer control to

the first command of the loaded micropro. grams. At the same time, the trigger 11 via the multiplexer 7 of the address is recorded either from the register of 3 micro-instructions or from the information input 20 of the device a sign of operation with the operational memory 2, the counter 4 switches to the mode of receiving information, and the address of the first micro-operator 40 is loaded into it

5 dyes to be executed

50

In all transition commands, the transition address is formed on adder 10 and multiplexer 9, depending on the value of the signal at the control input of multiplexer 9, either absolute, coming from multiplexer 7 or relative, and the increment is received through the second information input of adder 10 from the output of the multiplexer 7, and the base - on the first information input of the adder 10 from the outputs of counters 4 and 5.

When RW there are microcommands selected from the RAM block 2, the values of the corresponding bits of counters 4 and 5 coincide,

Claims (1)

Invention Formula A firmware control device containing a memory block, a memory block, a micro-command register and a decoder, the output of the memory block. connected to the first microinstructions register information input, the sync input of which is connected to the first clock input of the device, characterized in that, in order to improve speed, two address counters, multiplexers of the relative address of the microinstruction code and the transition address, summer, trigger, five elements AND, two elements OR, element NAND, and the second and third inputs of the device clock pulses are connected to the first input of the first element AND and the synchronous input of the trigger, the output of which is n Connected to the first input of the second element I and the input of the selection of the register of microinstructions, vto-30 input of the logical condition of the end of the information input and the output of which are connected respectively to the output of the operational memory and device output, the fourth input of the device clock pulses is connected to the first input of the third the element And the counting input of the first address counter, the output of which is connected to the address input of the RAM block and the input of the higher bits of the adder, the output of which is connected to the first information at the input of the multiplexer, the transition address, the output of which is connected to the information input of the first address counter, the input of the mode attribute of which is connected to the output of the first element OR, the output of the lower bits of the multiplexer, the transition address is connected to the information input of the second counter of the address, which output is connected to the first input of the lower bits The terminals of the adder and the address input of the block of permanent memory, the input address of the device transition address is connected to the first information input of the multiplexer of the relative address, the output of the small the lower bits of which are connected to the second information input of the multiplexer of the transition address and the second input of the adder, the first and second inputs of the device micro-commands download are connected to the first and second information inputs of the multiplexer of the micro-commands, the output of which is connected to the information input of the operational memory block, respectively; whose C-read is connected to the output of the first element AND, the output of the higher bit of the multiplexer of the relative address is connected to the information input of the trigger, you the element stroke is NOT connected to the first input of the second OR element, the output of which is connected to the second input of the third element AND, the output of which is connected to the counting input of the second address counter, the mode input of which is connected to the output of the fourth And element and connected to the second input of the second element And, the output of which is connected to the first input of the first element OR, the second input of which is connected to the output of the fifth element AND, five 0 the device load is connected to the second input of the second element {1LI and the first input of the fourth element I, the first output of the micro-register register is connected to the input of the decoder, the first output of which is connected to the second input of the fourth element I, the third input of which is connected to the first input of the fifth element I and the second the register of microinstructions, the second output of the decoder is connected to the second inputs of the first and fifth AND elements and the first input of the NAND element, the second output of which is connected to the third input of the first element AND the third output of the micro-command register, the fourth and fifth outputs of which are connected respectively to the control input of the transition address multiplexer and the second information input of the relative-address multiplexer, the control input of which is connected to the sixth output of the micro-command register and the micro-command code multiplexer input. 0 and Entry 1. Sawct ttaKDOKOftoff- days Iptiutrvs Mu / f-rokvnomd Zaeruzka address Off S cuemvuff I Pt & u J MeuiaipDamape .Craex / noff  Selector 9, (sou MHO mop 10 E11-typ-15, 9i, No..} In IM, par-not  MF (tsiSh1,5 I CvemwK I Selector Pamt  Element G8 or, J jait  Counting not Q I L shita-r mops Elements J3.15fl Abs. Rel. Selector 9, sumpator nofly fHus attributed / pelmoe adaoa intercept Record 6 counters f, 5 abresr peoehovo  Tpueeepff Scvemta / ff 5 Nepexi Address Record CvfmwKu.S -ZH fV ":" rv / Reading UmOff qmnd L. Fast., Tputttfiri f Reading (uj ffff J P (t / ipl1,2 Editor L.Pcholinsk Order 387/53 Circulation 673.Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 ut.Sf Compiled by M.Silin Tehred I.Popovich Proofreader E. Sirohman