SU1179308A1 - Interface for linking analog-to-digital converter with digital computer - Google Patents

Description

The first input of the OR element is the control input of the block, and the second input is connected to the information input and the information output of the block.

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The invention relates to the field of computer technology, in particular, to means of inputting measurement information into digital computers (CVM) and can be used in systems, automating nuclear-physical and other experimental scientific research, as well as industrial tests.

The purpose of the invention is to expand the class of tasks to be accomplished by providing the possibility of selecting events that satisfy one of many conditions in one cycle of operation.

FIG. 1 is a block diagram of the device; in fig. 2 - format of commands for event processing, placement of information selection programs V. microcommand mixing in microcommand memory cells; in fig. 3 is an example of the implementation of one bit of a comparison block; in fig. 4 is a block diagram of the algorithm of operation of the device under the control of a digital computer; in fig. 5 - time; a cycle diagram of the operation of the device for receiving, processing and recording incoming events in the buffer memory.

The device (Fig. 1) contains an intermediate register 1, block 2 input external parameters, the adder 3 ,. auxiliary memory 4, nerve address register 5, buffer memory 6, status word register 7, memory of micro-instructions 8, second address register 9, clock generator 10. coincidence unit 11, device information input 12, external parameter input 13, device, input 14 signal Ready device, output 15 signal Resolution

devices, device inputs / outputs 16, connecting the device with a digital computer, input-output 17 of the device correlation, connecting it with other similar devices for collaboration.

The coincidence unit 11 contains (Fig. 2) in each discharge switch 17, an element OR 18 connected via a matching resistor 19 to the power supply bus 20. positive polarity.

The device works as follows.

From an ADC (not shown), the event code is written to intermediate register 1 and later

to a buffer memory 6, where an array of measured data is accumulated. In the second stage, events are selected that represent the article. For this is provided auxiliary

memory 4, the capacity of which corresponds to the number of possible values of event codes. The event code is used as the main part of the auxiliary memory address 4, and in the cells corresponding to each

the address is preliminarily recorded by means of a digital computer that the usefulness of the event is recorded, for example, 1 in the cell is fixed, that the event is of interest, and O is not.

To register multidimensional events using several ADCs, each of which is associated with its device, a block 11 is provided, which compares the utility features generated

auxiliary memory 4 of each device and, if they match, generates a common signal for all blocks.

Permanent memory is used as the memory of 8 micro-commands, since for a particular experimental system the set of processing programs is usually unchanged, as an auxiliary memory is operational, as during each experiment there can be many times the demand for changing operands.

FIG. Figure 2 for example shows memory 8, consisting of 32 cells with addresses from 00000 to 11111. It is used to host four very short programs (since the processing in the device is performed on a time scale determined by the intensity of the incoming event flow). The memory is divided into -8 sections of 4 hexes so that the 1st and 5th yiiacTKH. used for the first program, the 2nd and the 6th. for the second and t, d. The first program determines the unconditional recording of data from intermediate register 1 to the buffer memory 6. It, as seen in FIG. 2, consists of a single command placed in a cell with the address 00000. The second program controls the recording of useful events in the channel to the buffer memory 6. It consists of three commands placed in 5 and 6th and 22nd cells. The processing cycle checks the usefulness of the event. If it is not presented / live or not, then record D buffer memory 6 is not made, and the program ends (on command from the 6th cell), if it is, then the record. is executed and the program ends there. The third program differs from the second in that the writing to the memory 6 is performed in incremental mode. This program can be used if memory 6 allows such a mode. The fourth program is designed to search for a sign of an event of interest due to double access to memory 4. The address of the next command is determined by the state of register 5, which is formed by a set of signals from register 7 to the basic input (bits 3 and 4) from block 11, the pa inputs of the modification and from memory 8 in the counting mode to the control input (in bits 1 and 2). The address of the operand in the auxiliary memory 4 is determined by the state of register 9, which is formed by the scoop of signals at the corresponding inputs from register 1 (determines the cell in the selected memory page), block 2 and memory of 8 microcommands (the page is defined) . The block diagram of the device operation under the control of a digital computer is shown in FIG. 4. To prepare the device for accumulating information, register 7 is first reset to its initial state, as a result of which register 9 is reset and transferred to counting mode, and its modification inputs are blocked. By this, memory 4 is prepared to receive data from a digital computer. After filling in memory 4 with a list of events of interest, the next command of the digital computer registers 7 to the next state, which enables unlocking the inputs of the modification of register 9, putting it into operation, setting the operation mode of blocks 2 and 11, and selecting the processing program Event setting base (starting address). The next command CVM register 7 outputs the signal 15 for the resolution of the ADC, opens the clock generator 10 for the signal Readiness 113 ADC, issues a resolution to register 5 for executing the program for processing events arriving at the inputs 12 and 13 of the device. The time diagram (Fig. 5) shows the cycle of operation of the device for receiving, processing and recording incoming events in the buffer memory 6 (for example, the second fMMbl). 08L (In case of post-termination from the LII code of the event to the input 12 n simultaneously (or in advance) one or several signals of extra parameters at the input 13, the information from the register passes to the adder 3 and simultaneously to the register 9, and I1 formation from block 2 to the register 9. Block 2 performs the transmission and signaling of the signals input to input 13. There are two possible operating modes depending on the control signal generated by the status word register 7. The first is the reception of one of the mutually exclusive signals, the second is the reception of several non-exclusive signals. In block 2, for example, a permanent memory can be used in which the permissible states of external signals are encoded. When information arrives at register 9 from memory 4, the sign code of the recorded event is read, which indicates that this event is of interest or not (zero code) .This device is supplied to block 11, which is (Fig. 3) a set of OR elements implementing HED I. The input-output of this block is used to connect to identical blocks in other interfaces that serve ADC to measure other parameters of this event (in a multi-dimensional analysis). In a one-dimensional analysis, the connection with the highway with the aid of the switches 17 is broken, and the information passes to the adder 3, mine unit 11. The masking signal on the control input from the register 7 always passes the feature code to the control output of unit 2 to modify the register 5 In multidimensional analysis (the joint operation of several devices), two options are possible. In the first case, the coincidence of the same feature codes for all devices is determined. This mode differs from autonomous operation only in that through switches 17 are interconnected - the inputs / outputs of all interface devices. In the second, the information recorded by this device is to be recorded in memory 6, if its utility is recorded by all other coincidence devices. For this, the signal at the control input of block 2 masks the passage of a code of attributes to the control output. The feature code generated by the memory 4 of this device can be used to modify the data from the ADC, for example, to change the page in the buffer memory 6.

When a clock signal arrives at input 14 and generator 10, the readiness from the ADC, the command passes to the memory output of 8 micro-instructions and is executed in accordance with the program. At the end of the program, the register 7 of the state word is transferred to the corresponding state, in which the device is prepared to receive the next event, i.e. the Resolution signal is given again, the generator 10 is blocked, opens Fi8. one

from its input 14, register 5 is brought to a working state.

Thus, the device provides an extension of the class of tasks by performing the functions of preliminary processing of experimental data entered into a computer. This will increase the speed

Q data processing and measurement systems effectiveness.

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Claims (2)

(54 1. A DEVICE FOR PAIRING ANALOG-DIGITAL CONVERTER WITH A DIGITAL COMPUTER MACHINE, containing an intermediate register, the input of which is the information input of the device, an input block for external parameters, the information input of which is an input for setting external parameters of the device, a buffer memory, a status word register and auxiliary memory, the inputs and outputs of which form the input-output of the device, the adder, the memory of microcommands, the first and second address registers and the clock generator, the start input of which is with the input signal '' Ready '' of the device, and the output is connected to the micro-command memory clock input, the address input of which is connected to the output of the first address register, the first, second, third and fourth micro-command outputs are connected respectively to the control input of the first address register, page modification input the second address register, the control inputs of the buffer memory and the register of the word property, the first, second, third, fourth and fifth bit outputs of which are connected respectively to the control input h buffer memory, the basic input of the first address register, the control input of the second address register, the enable inputs of the clock generator and the first address register, connected to the output of the signal '' Resolution '' of the device and with the control input of the input block of external parameters, the output of which is connected to the input of the modification the second address register, the address input of the auxiliary memory is connected to the output of the second address register, the output of the adder is connected to the information input of the buffer memory, the control output which is connected to the data input of the status word register, characterized in that, in order to expand the class of tasks. devices by providing the ability to select events that satisfy one of many conditions, za and one clock cycle, a block of coincidence fixing is introduced into it, and the input-output of the block of coincidence fixing is the input-output of the correlation of the device, and the information input is connected to the output of the auxiliary memory, information output - with the first input of the adder, the second input of which is connected to the information input of the second address register and with the output of the intermediate register, the control input of the matching block is connected with an additional bit output of the register of the status word, and the control output is connected to the input of the modification of the first address register. 2. The device according to π. 1, and the fact is that the coincidence fixing block contains an OR element, a switch and a terminating resistor in each category, the output of the OR element being the control output of the block and connected through the switch to the input / output of the block, and through a terminating resistor - with a bus power supply, positive polarity, S and ..., 1179308, the first input of the OR element is controlled with the information input and the informing input of the block, and the second input is the communication output of the block.