SU1591027A2 - Device for interfacing cental processor with group of peripherals - Google Patents

Description

The invention relates to computing, can be> used to organize the exchange of information between digital processors

The invention relates to computing, can be used to organize the exchange of information between processors of digital computers of multi-machine complexes and is an improvement of the invention according to the author. No. 1260968.

The aim of the invention is to improve the reliability of the device by ensuring the separation in time of the processes of writing and reading.

The drawing shows a functional diagram of the device.

The device contains a central processing unit (CPU) 1, a shift register '2, the first counter 3, the first switch 4, the first 5 and the second 6 blocks of memory, the second counter 7, the trigger 8, the multiplexer 9, the synchronizer 10 ,.

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computers of multi-machine complexes and is an improvement of the invention auth.St. No. 1260968, The purpose of the invention is to improve the reliability of the device by ensuring the separation in time of the processes of recording and reading. interrupt, interrupt mask register, mask and end exchange register, exchange indication register, two elements OR, AND element, two groups e

elements I. 1 Il.

second switch 11, register 12, pulse generator 13, peripheral processors 14 and 15, buffer register

16, AND 17, interrupt register 18, interrupt mask register 19, AND 20 group of elements, OR element. 21, register 22 of the end of exchange indication, register 23 of the end-of-exchange mask, AND 24 group of elements and OR 25 element.

The device works as follows.

The transmitted data from CPU 1 is sent to register 2, from the output of which in the form of a sequential code for-_ are written to the first 5 or second 6 blocks of memory depending on the state of trigger 8, which is set by CPU 1, and the information is expanded in memory by zones, attached to peripheral processors 14 and 15, with

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using the first counter 3 · Such a construction of a write-to-memory scheme allows to form a sequential code centrally for all processors. Having counted a specified number of words, the first counter 3 issues a signal from the element And 17, to another input of which a permit signal comes from the CPU 1. From the output of the element 17, the signal goes to the corresponding register bit 18, the output of which at the resolution value on register 19 is signal "Interruption" through the corresponding elements of AND 20 and OR 21 is fed to the input of CPU 1, indicating that the recording in block 5 (block 6) is completed and it is possible to issue information to the appropriate peripheral processor and simultaneously to the enabling input of register 12, blocking possible unauthorized access of the peripheral processor to the register. The CPU 1 by applying the corresponding signals to the second counter 7 and the trigger 8 sets the information output mode to the peripheral processor. The information is read from a memory block under the control of a 7 ”counter operating at a fixed frequency of the synchronizer 10. Information from the memory block connected to the reading by the trigger. 8, alternately from each memory zone is read as Single bits through multiplexer 9 and switch 11 to the buffer register 16. After writing the last word, the signal from the signal output of the register 16 goes to the corresponding input of the peripheral processor and simultaneously to the input of register 12, removing the lock. After that, information from register 16 is rewritten to register 1.2, where it is stored for the time required to load processors 14 and 15.

After the end of the reception of information from the peripheral processor to the corresponding discharge register 22 receives the signal "End ^of exchange ¹ ". With the enable signal on register 23, the signal from register 22 through the corresponding elements AND 24 and OR 25 is fed to the corresponding bit of register 18, from the output of which through the chain of elements AND 20 and OR 21 is fed to the corresponding input of CPU 1, after which the data transmission cycle is repeated.

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Claims (1)

Claim Device for interfacing a central processor with a group of peripheral processors according to auth.St. H * 1260968, characterized in that, in order to increase reliability by ensuring the separation in time of the write and read processes, a buffer register, an interrupt register, an interrupt mask register, an exchange end mask register, an end indication indicator register, and , two elements OR, two groups of elements AND, the first input of the element AND being the input of the device for connecting to the third address output of the central processor, the information inputs of the interrupt mask register and the register of the exchange end mask are the device inputs for connecting respectively the fourth and fifth address outputs of the central processor, the output of the first OR element is connected to the first enable input of the register and is the device output for connecting to the central processor interrupt input, the group of information inputs of the exchange end indication register forms the device input group To connect to the exits of the exchange of peripheral processors of the group, the output of the buffer register is connected to the second enable input of the register and. is the output of the device for connecting to the ready inputs of the peripheral processors of the group, the group of information outputs of the second switch is connected via a buffer register with a group of information inputs of the register, the output of the first counter is connected with the second input. the home of the AND element, the output of which is connected to the first information input of the interrupt register, the output group of which is connected to the first inputs of the AND elements of the first group, the second inputs and outputs of which are connected respectively to the output group of the register of the interrupt mask and the input group of the first OR element, group of outputs of the register masks of the end of the exchange and the register of indication of the end of the exchange are connected respectively with the first and second inputs of the elements of the second group, the outputs of which are co5 1591027 ⁶ are united with the group of inputs of the second element with the second information input of the interrupt register. cop or / whose output is connected