SU947910A2 - Logic storing device - Google Patents

Description

The invention relates to computing and can be used in the construction of storage devices and processing of discrete information.

According to the main auth. 649037 a logical memory device is known that contains groups of one-bit memory blocks, each of which contains the main memory blocks, whose address inputs are connected to the address buses, the write and read inputs are connected to the write and read buses of the same name, the gates are connected to the bus general gates, information inputs and outputs are connected respectively to the outputs of the input and outputs of the output registers, as well as an auxiliary memory block, group gates buses by the number of one-bit groups memory blocks, gating control bus, interrogation bus, group gating characteristic bus, constant input bus and indication bus connected to the information output of the auxiliary memory block of the last group, each of the group gating buses is connected to the gates of the main memory blocks. ti and

The auxiliary memory block tweying input of the corresponding group connected to the gating control bus, the write input of each auxiliary Psm unit, is connected to the write and read buses, the read inputs of the auxiliary memory blocks are connected to the polling bus, the group gating bus is first

10 groups of memory blocks are connected to the group gating bus, the group gates bus of each subsequent group of memory blocks is connected to the information output

15 of the auxiliary memory block of the previous group, and the information and address inputs of the auxiliary blocks psm m are connected respectively to the input bus of the constant and to the address

20 tires 1.

A disadvantage of the known logical storage device is that it cannot be used to perform editing operations for information and priority service of requests for the exchange of information.

The purpose of the invention is to expand the field of application of the logical memory device, which will allow the device to be used for performing information editing operations and priority servicing of forwarding requests. This goal is achieved due to the fact that the known logical memory device contains an additional register and an additional control bus, the information inputs and outputs of the additional register are connected respectively to the information outputs and the gate inputs of the main blocks, and the control input of the additional register is connected to an additional control bus, which is one of the control inputs of the logical storage device. The drawing shows a diagram of the proposed logical storage device. The device contains groups of 1 one-bit memory blocks, each of which contains the main 2 memory blocks and the auxiliary 3 memory blocks, the input register 4, whose outputs are connected to the information inputs of the main memory blocks 2, the control input to the control The bus 5, and the inputs 6 are the information inputs of the logical memory, the output register 7, the inputs of which are connected to the information outputs of the main memory blocks 2, the control input is connected to the control bus 8, and the output 9 are information output A logical memory as well as an additional register 10, inputs 11 of which are connected to the information outputs of the main memory blocks 2, and outputs 12 to the gate inputs of the corresponding main memory blocks 2. The address inputs of memory blocks 2 and 3 are connected to address buses 13. The write and read inputs of the main memory blocks 2 are connected to the write and read 14 buses of the same name 15. The write input of the auxiliary memory blocks 3 is connected to both the write bus 14 and and to the read bus. Read inputs. Auxiliary 3 memory blocks are connected to the poll 16. The gate inputs of the main memory blocks 2 are connected to the common gate bus 17 and to the corresponding group gate bus 18, and the gate input of each auxiliary memory block 3 is connected to the corresponding gate bus 19. The group gating bus of the first group 1 is connected to the group gating feature bus 20, and the information output of the memory unit 3 of the last group 1 is connected to the indication 21. The information inputs of the auxiliary memory units 3 are connected to the constant input bus 22. Logical storage device has four modes of operation: work with a full word, group work, editing and priority service of requests. Assume that, prior to starting work, all cells of the 3 memory blocks are written with zeros. Writing or reading operations in memory blocks 2 and 3 occurs only if they are in the active state. The transition of each of the blocks 2 and 3 of the memory to the active state is possible only by a signal arriving at the gate input of these blocks. After performing write or scans, memory blocks 2 and 3 go to a passive state. Control signals to buses 5, 8, 11, 13 and 17, 19, 20 and 22 are provided from a control unit (not shown). The operation of the device in the full word mode is as follows. In the first clock cycle, a control signal is received on the common gating bus 17, which brings all the 2 memory blocks to the active state. In the second cycle, the control signals are supplied to the address buses 13 and one of the write 14 buses or read 15 buses. If the second clock showed a control signal on the write bus 14, then in the address section of the memory blocks 2 corresponding to the address code on the address buses 13, the contents of the input register 4 were recorded. If, in the second cycle, the control signal arrived at the read bus 15, then from the address section of the memory blocks 2 corresponding to the address code on the address buses 13, information was read and recorded in the output register CTR 7. At the end of the second clock cycle, the full word operation ends. The operation of the logical storage device in group mode is as follows. Suppose that when performing a write operation, the information received at the inputs 6 of input register 4 has a byte format and is recorded by the signal on control bus 5 into all groups of bits of input register 4 corresponding to groups 1 of memory 2, and performing a read operation, the information bytes read in any of the groups 1 are entered by a signal in the control bus 8 into a certain group of bits of the output register 7 for outputting information of the byte format. In the first clock cycle, a strobe signal is applied to the gate control bus 19.

transferring all the 3 memory blocks to the active state. In the second cycle, when performing a write operation on signals input to the polling bus 16 and to the control bus 5, the address section of the memory blocks 3 determined by the address code on the secondary buses 13 is polled and the byte of information received in the same cycle is recorded to inputs 6, to all groups of bits of the input register 4, corresponding to the group 1 of 2 memory blocks.

If a unit is recorded in any block 3 of the vTH memory in the interrogated address section, it is read and the signal from the information output of this memory block 3 goes to the group gating bus 18 of the subsequent group 1 and causes the active state of all blocks 2 and 3 memories of the subsequent group 1 ..

in the third cycle, the control signals are supplied to the address buses 13, to the constant input bus 22, and to the write bus 14. As a result, in the address section defined by the address code on address buses 13 of that group 1, blocks 2 and 3 of the memory of which are in the active state, the contents of the corresponding group of bits of the input register 4 will be written into blocks 2 of memory and units arriving via the constant input bus 22 into memory block 3.

Thus, the presence of a unit in one of the address sections of memory block 3 indicates that the operation is performed in this address section of memory blocks 2 of the corresponding group 1.

Repetition of the considered three-stroke sequence ensures sequential execution of operations in consecutive groups 1, namely, writing sequentially incoming information bytes in the same address section of consecutive groups 1, or reading information bytes from the same address section of sequentially located groups 1.

Information is read out with destruction, as a result of which in any address section of all blocks 3. A memory cannot contain more than one unit, which ensures that the operation is performed only in one of groups 1.

The difference in the operation of a logical storage device when reading information in group mode from working in group mode when recording information is that in the second cycle there is no signal on the control bus 5 of the input register 4 and in the third cycle there is also no signal on the write bus 14 and signals to read bus 15 and to control bus 8 of the output register. 7 ..

As a result, a read operation is performed in memory blocks 2 in the active state, and the presence of a signal on the control bus B of the output register 7 ensures that the read information from the information outputs of memory blocks 2 of any of groups 1 is inserted into a certain group of bits Dov output register 7.

Information output from the output register 7 at the output of the tire 9 is performed in the first cycle. The appearance of a signal on the display bus 21 connected to the information output of memory block 3 of the last group 1 in the second clock cycle means that the formation of a complete word from the incoming information bytes during the write operation is completed in this address section or the dissolution of the stored address cross-sectional storage of the full word to bytes when performing a read operation.

According to the signal on the display bus 21, the control unit generates a signal on the bus 20 of the group gating feature in the same cycle, transferring the active state blocks 2 and 3 of the memory of the first group 1. At the same time, the address code is also changed, on the address buses 13.

In the event that the operation of the logical memory in the group mode ends after the formation or disintegration of the complete word is completed, the control unit additionally sends a signal to the group gating bus 20 in the second cycle from the first series in three cycles in a subsequent transition to the group mode. The operation of the logical memory in the remaining three-cycle series does not differ from that considered.

Consider the operation of a logical storage device in the information editing mode and the example of performing such editing operations as masking, replacing groups of bits, performing a logical operation on a group of bits.

We assume that R cells (where n is the total number of cells of a logical storage device) contain masks that are used when performing the operations listed above.

The operation of the logical memory of its device when performing a masking operation proceeds as follows. In the first cycle, a signal arrives on the general gating bus 17, which puts all the 2 memory blocks in an active state. In the second cycle, control signals are sent to address buses 13, read bus 15 and control bus 11. After the second clock, a mask containing zeroes in the group of K bits will be entered into additional register 10 (where m is the word dannoh) . In this case, the control signals from the outputs 1 of the auxiliary register 10 will translate into the active state all the blocks 2 of the memory, except those containing a group of K word bits. In the third cycle, the control signals are fed to the address buses 13, read bus 15 and bus 8. At the end of the third clock operation, the masking operation ends and the output data register 7 contains the data word, the group of K bits of which contains zeros. The operation of the logical memory device when performing the operation of replacing a group of bits. Control signals c. The first two clocks are served in the same sequence as during the masking operation. After the second clock cycle, an additional register 10 is entered into a mask containing the units in the group of bits to be replaced. In this case, the corresponding blocks of 2 memory go into active state. In the third cycle, the control signals arrive at the address buses 13 and the write bus 14. After that, the group in the data word is needed is replaced with -adrived from the input register 4. The operation of the logical storage device when performing the logical conjunction operation. The control signals in the first two clock cycles are given in the same way as when performing a masking operation and replacing the bit groups. After the second clock cycle, one of the operands is written to the additional register 10. At the same time, the active state of the transition is t blocks 2 of memory, for strobe inputs of which single signals are received from the output buses 12 of the additional register 10. In the third cycle, the control signals go to the address buses 13, the read bus 15 bus 8.- At the end of the third one, the output register 7 records the result of the operation of the conjunction. In the priority request mode, the logical storage device works: as follows: Suppose that one by one alres in the logical storage device, for example, at the zero address, the mask of the serviced request is stored, equal to the inverse of the priority word of the external device. The request codes come from external devices to the address buses 13 of the logical storage device whose address sections store the priority words of external devices. When a request code from an external device arrives at address buses 13, the logical storage device begins to process the request. In the first control cycle, the signal arrives on the general gating bus 17 and switches all the 2 memory blocks to the active state. In the second cycle, the control signals go to the read bus 15 and to the bus 11. In this case, the additional register is entered into the priority word of the incoming request and the memory blocks of 2 memories go to which the single signals from the output buses 12 of the additional register go to the active state 10. In the third cycle, control signals are sent to address buses 13, read bus 15 and bus 8. After the third clock cycle, output zero is entered into output register 7 if the priority of the serviced request is higher than or equal to the priority of the incoming request and entered but at least one unit otherwise. In the first case, the maintenance of the previous request is continued, and in the second, the maintenance of the previous request is interrupted, the service of the incoming request is started, and in the fourth cycle the control signals go to bus 5, while a constant is received in the input register containing units in all bits, a common gate bus 17, address buses 13 and a write bus 14. In this case, all blocks 2 of the memory go into the active state and units are recorded over the zero address section. In the fifth cycle, the control signal is fed to the address buses 13 and the write bus 14. After that, the zero request address section contains the mask of the incoming request, equal to the inverse of the contents of the additional register 10. At the end of the fifth cycle, the formation of the mask of the serviced request is completed and the logical memory goes into the waiting mode of the new request. Thus, the introduction of an additional register and an additional control bus allows to expand the scope of application of the logical storage device due to the possibility of performing a number of additional operations, which indicates the achievement of the set goal.

Claims (1)

1. USSR author's certificate No. 649037, class. SIS 15/00 ,. 1975 (prototype).