SU1762309A1 - Device for connecting two processors - Google Patents

Abstract

The invention relates to computing and can be used to build high-performance multiprocessor computing systems. The purpose of the invention is to increase the exchange performance. To this end, a device containing a bus driver and an I element is inserted into a block of n bi-directional groups of bus drivers, a group of bus address drivers, synchronization register, bus write driver block, write decoder, read decoder, bus sign driver, g Records element AND permission of the exchange, element AND AND NOT records and the element is NOT 3 or

Description

The invention relates to computing and can be used to build high-performance multi-processor computing systems.

The purpose of the invention is to increase the exchange performance.

Figure 1 shows a functional diagram of an apparatus for interfacing two processors; Fig. 2 shows an embodiment of the memory of the central processor; FIG. 3 shows an example of the implementation of the memory of the I / O processor.

The device for interfacing two processors (see FIG. 1) contains a block 1 of bidirectional groups of tire drivers consisting of 1.1-pth 1.n bus-driver groups from the CPU and from the first 1. (n + 1) -n-1 1 2n groups of tire formers from PVV, each group of tire formers (i - 1, n and

n + 1.2p, respectively) forms the i-th bidirectional group of bus drivers; block 2 bus write drivers, including the first 2 1-p-y 2 p bus write drivers, group 3 bus address drivers; synchronization register 4, write decoder 5, read decoder 6, inversion bus driver 7, write flag bus driver 8, element 9 AND, element 10 AND NOT to allow exchange, element 11 AND NOT write and element 12

In addition, FIG. 1 denotes a group of 13 information highways of the CPU, including the first 13.1th of a 13.p. informational highways; information line 14 PVV, address line 15 PVV, input 16 of the device recording micro-operation, input 17 of the device handling micro-operation, sign 18

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WITH

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interprocessor exchange of the device, input 19 of the exchange request from the UIP device, synchronous input 20 of the device, input 21 of the exchange request from the CPU of the device, input 22 of the exchange of the exchange from the CPU of the device, address CPU 23; a group of 24 recording signal outputs, including the first 24.1-nth 24.n write signal outputs; a device writeout output 25, a device callback output 26, an exchange request output 27 from the UIP device, an exchange enable output 28 from the device CPU, an exchange request 29 from the device CPU.

The inputs-outputs of the first group of information inputs-outputs of the block 1 of bidirectional groups of bus drivers by means of n information highways 13.1-13.p are connected to the group 13 of information highways of the CPU of the device. The second group of information inputs and outputs of the block 1 of bidirectional groups of bus drivers is connected to the information highway 14 UIP.

Address highway 15 PVV high-order bits through a group of 3 bus address formers are connected to address line 23 of the CPU.

The request input 21 and the exchange enable input 22 from the CPU of the device are connected respectively to the first D1 and second D2 information inputs of the synchronization register 4, the sync input C of which is connected to the synchronous input 20 of the device.

The input 19 of the exchange request from the PVV device is connected to the first input of the element 9 I, the output of which is connected to the output 27 of the exchange request from the PVV. The input 16 of the micro-operation of the recording device is connected to the first control inputs of the write decoder 5 directly and the read decoder 6 via the element 12 NOT, with the information input of the bus driver 8 of the record indication and with the first input of the element 11 AND-NOT write.

The input 18 of the interprocessor exchange attribute of the device is connected to the second control input of the read decoder 6 and the second inputs of the AND element 9 and the AND-NOT element 11.

The first Q1 and second Q2 outputs of the synchronization register 4 are connected to the exchange request outputs 29 from the device CPU and the first input of the N-10 element to enable the exchange. The output of element 9 I is connected to the second input of element 10 of the exchange resolution AND – NOT, the output of which is connected to the output 28 of the exchange resolution from the CPU of the device and connected to the inverse control inputs of the tire drivers (2.1-2.p.) of group 2, bus formers 7 inversion and 8 sign write and group 3 bus formers address.

The synchronous input 20 of the device is connected to the second control input of the write decoder 5, the inverse outputs of which are connected to the information inputs of the bus driver 2.1-2.P recordings of group 2 through a group of information inputs of the block 2 bus recorders.

The outputs of the bus drivers 2.1-2, n records of group 2 are connected to the outputs 24.1-24.p signals of the group of 24 outputs of the signal recording device.

The microprocessor input 17 of the device is connected to the information input of the bus inverter 7 and to the third control inputs of the write decoder 5 and 6 readings.

The lower bits of the address highway 15 PVV are connected to groups of information inputs D decoders 5 records and 6 reads. The inverted outputs of the bus formers 7 of the call and 8 of the write flag are connected to the outputs 26 of the call signal and 25 sign of the device record, respectively.

The inverse outputs of the read decoder 6 from the first to the nth are connected from the first to the nth control inputs of the block 1 of the bidirectional groups of bus drivers, (n + 1) -th control input of which is connected to the output of the AND-11 element of the write.

Block 1 of the bidirectional groups of tire formers contains 2n bidirectional groups of tire formers, each of which consists of the group 1.i (i 1, π) of the tire formers from the CPU and the group 1.i (i n + 1.2n) of the tire formers from the PVV. ,

The outputs of each group 1.i (I i + 1,2n) bus drivers from UIP are connected to the information inputs of the corresponding group 1.1 (i 1, n) bus drivers from the CPU and form the corresponding information highway 13.1 (i l7n) of group 13 information CPU highways connected to the first group of information inputs-outputs of the block 1 of bidirectional groups of bus drivers, the second group of information inputs-outputs of which are connected to the outputs of each group 1.i (i 1, n) of bus drivers and to the inputs of each group 1 .i (i i nI, 2p) tire forms rovers from UIP. The control inputs of the block 1 of the bi-directional groups of bus drivers from the first to the n-th are connected to the inverted control inputs of the groups of bus drivers from the CPU with the first 1.1

on the n-th 1.n respectively. (n + 1) -th control input of the unit 1 of bidirectional groups of bus formers is connected to the inverse control inputs of all n groups 1. (n + 1) -1.2p for bus formers from urea,

To clarify the principle of operation of the device for interfacing two processors, Fig. 2 shows an example of the construction of a central processor memory, the multiplicity of the information format of which is equal to n with respect to the format of the information of the PVV.

The CPU memory (see FIG. 2) is a group of 30 RAM blocks of the CPU, i.e. consists of i blocks 30i (i 1, p) of the RAM, and also contains the element 31 AND-NOT read; block 32 of information input tire drivers of the operating memory of the CPU, consisting of the first 32.1-th-th 32.n groups of bus drivers of the block; block 33 of information output bus formers of the operating memory of the CPU, consisting of the first 33.1-th-th 33.p groups of bus formers of the block; group 34 addressable CPU bus formers; a block 35 of CPU write bus drivers, consisting of the first 35.1-p-th 3. of a bus write driver, the outputs of each of which are connected to the power bus through corresponding resistors 36.1-36. bus driver 37 inversion CPU, the inverse output of which through a resistor 38 is connected to the power bus; a bus driver 39 of the CPU write attribute, the inverse output of which is connected via a resistor 40 to the power bus. In addition, in Fig. 2, the information highway 41 of the CPU is designated, the bit size of which is n times the size of each of the n information highways 13.i (i 1, n) of group 13 of the information highways of the CPU; a group of 42 address inputs from the CPU; a group of 43 inputs of CPU recording signals, which includes the first 43.1-pth 43.p inputs of CPU recording signals, CPU recording indication input 44, CPU access input 45 and CPU access control input 46.

The outputs of the bus formers 35.1-35.p recording unit 35 inputs connected to the inputs 43.1-43.p group 43 of the inputs, and the outputs - to the outputs 24.1-24.p group 24 outputs of the device and to the recording inputs, respectively, blocks 30.1-30.p operational memory CPU.

The group 34 of address bus drivers of the CPU is connected to the group of 42 address inputs from the CPU, and the outputs are connected to the address highway 23 of the device and to the address inputs of the 30.1-30.p blocks of the CPU memory bus.

The bus driver 3 / S.P. CPI is connected to the input 45 of the CPU activation and the inverse output - to the input signal of the device, to the inversion inputs of the memory blocks 30.1-30.p and the inverted input of the 31 AND-NAND element, the output of which connected to the inverse control inputs of the groups 33.1-ZZ. bus drivers.

The bus driver 39 of the CPU write feature of the input is connected to input 44 of the CPU write feature, and the output is connected to the device writing feature output 25, with the inverse control inputs of the 32.1-32. bus drive groups and the direct input of the AND 31 element.

The information outputs of the 30.10 30.p. memory blocks are connected to the information inputs of the groups 33.1-33 of the tire drivers, respectively. The outputs of groups 32.1-32.p bus drivers are connected to the information inputs of the blocks

5 30.1-30.p memory, respectively. The outputs of groups 33.1-ZZ. Bus drivers and information inputs of groups 32.1-32. Bus drivers are connected in pairs with each other and with information channels 13.1-13.p of group 13 of the information highways of the CPU. connected to the device and to the information highway 41 CPU.

The main memory access control input 46 of the CPU is connected to the inverse control inputs of bus formers 35.1-35.p of block 35, groups 34 of address bus formers of CPU and bus formers 37 for CPU reversal

0 and 39 signs write CPU.

Fig. 3 shows an example of a PVV RAM block 47, which is connected to information address 14 UIP by information inputs-outputs, and by address inputs 15 to UIP 15. The access and write inputs of the PVV RAM 47 are connected to the inputs 48 of the access and 49 records from the UIP, respectively.

0 Since the size of the information

PWV is a multiple of CPU information. then it is obvious that the higher bits of the addresses of the highway 15 are transmitted to the output of the device for selecting the addresses of the cells in blocks 30

5 CPU memory, and low-order bits through decoder 5 and 6 provide work with the corresponding groups (from the first to the nth) bits of the CPU format information.

In addition, since the exchange request output 29 from the CPU is similar to one-bit

exit 27 exchange request from the PVV, so the register 4 is one-bit.

The bit width of the information highway 14 PVV is a multiple of the bit width of the information highway of the CPU trunk, the degree of multiplicity is n, therefore the bit width of the highway 14 is equal to the bit width of each of the highways 13.1-13.p. When transmitting information from the PVV to the CPU, information from the trunk 14 is transmitted to each of the highways 13.1 ... 13.P, and in which of the n blocks 30 it will write down the lower-order address bits from the trunk 15 using the decoder 5.

Before describing the operation of the device as a whole, we describe the purpose and operation of its individual elements and assemblies, as well as the elements and assemblies of the operational memory of the CPU (see FIG. 2) and the PVV (see FIG. 3) given for example,

Block 1 of the bidirectional groups of bus drivers is designed to transfer information from the CPU to the UIP and vice versa. When transmitting information to the PVV from the CPU (from the information highway 41 CPU (see figure 2)), i.e. groups 13 of the CPU information highways to the information highway 14 UIP, the outputs of only one of the n groups 1.i (i l7n) of the bus drivers from the CPU are in an active state, namely, that controlled by a low level signal from one of the n inverse outputs decoder 6 readout.

When transmitting information from the PVV to the CPU, the outputs of all n groups 1. (n + 1) -1.2p bus drivers from the PVV are in an active state under the control of a low level signal from the output of the AND-11 recording element. In this case, information from the information highway 14 of the PVV enters each information highway 13.i (i Tn) of the group 13 of the information routes of the CPU.

In those cases when there is no transmission of information from the highways 13.i (i 1, p) of the CPU to the main 14 of the PVV or vice versa, which corresponds to the absence of a low level of signals at the inverse outputs of the decoder 6 readout and element 11 AND-NOT the records, outputs of all groups 1.1-1.2p of the bus formers of the block 1 are in the third (high-impedance) state. At the same time, the operation of the CPU and the UIP takes place in parallel and independently from each other.

Block 2 of the write bus driver is designed to transmit 24 outputs to the group, i.e. to memory CPU low level of recording signals from the inverted outputs of the write decoder 5, if the output element 10 AND-NOT formed low

signal strength. Only one of the bus drivers 2.i (i 1, n) of block 2 can be transmitted at the same time point of the recording signal low level. At

5, the high level of the signal at the output of the element 10 is NOT the outputs of all bus drivers 2.i (i 1, n) of block 2 is in the third, i.e. high impedance state.

10 Group 3 bus address formers is designed to transfer address codes from address main 15 UIP to address main line of the CPU if the output of the element 10 is NOT a low signal level.

15 Otherwise, the outputs of the group 3 bus address drivers are in a high-impedance state.

Synchronization register 4 is designed to synchronize the interaction of the CPU and

20 PVV, i.e. for linking the occurrence of CPU signals at the exchange request inputs 21 from the CPU and 22 exchange permissions from the CPU to the clock grid of the UIP. Therefore, a synchronization signal arrives at the device synchronization 20 - one of a series

25 clock pulses UIP, determining the clock pulses, synchronizing the work UIP.

Binding is perception (and therefore no impact).

30 devices of these two signals only at the time of the leading edge of the sync signal from the UIP to the synchronous input 20 of the device.

Decoder 5 records designed

35 to form a recording signal for the CPU memory (when transmitting information from the PVV to the CPU) only for a portion of this memory having an information format equal to the format of the PVV information. Corresponding part

40 (section) of the CPU memory is determined by the code specified in the lower-order bits of the address code on address main 15 UIP. The recording signal (low signal level) on the corresponding inverse output of the decoder 5

45 records are formed only when three conditions are met: the presence of a micro operation of the input 17 of the device, a micro operation of the record at the input 16 of the device, and a synchronization signal on the synchronous input 20 of the device.

In contrast to the write decoder 5, the read decoder 6 is designed to transmit information from the CPU to the UIP. In this case, the trunk section 41 CPU or section

The 55 RAM of the CPU is selectable to transfer information from the CPU to the UIP, specified by the lower code bits on the address highway 15 of the UIP, and the moment of transmission of this information (opening one of the groups 1.i (i .n) of the CPU bus generators) is determined by The following three conditions: the presence of a micro-operation of addressing at the input 17 of the device, the absence of a micro-operation of recording at the input 16 of the device and the presence of a signal at the input 18 of the sign of interprocessor exchange of the device. The bus driver 7 is used to transmit (with inversion) the CPU memory access signal from the UIP input to input 17 of the device micro-operation, in the presence of a low-level signal at the output of the AND-10 element allowing the exchange. Otherwise, the inverted output of the bus driver 7 inversion is in a high impedance state.

The bus driver 8 of the write attribute is intended to generate a low level signal at the output 25 of the device record attribute at the moment when the recording microoperation signal arrives at its input 16, in the presence of a low level signal at the output of the 10-AND-NOT exchange exchange element. Otherwise, the inverted output of the bus driver 8 of the write flag is in the third state.

Element 9 I is designed to form at the output 27 of the interchange request request message from the UWB device the exchange request signal from the UIP to the CPU when the exchange request signals to the CPU and the sign of interprocessor exchange are received from the UIP to the inputs 19 and 18 of the device. In addition, the signal from the output of element 9 I is one of the conditions for the operation of element 10 AND-NOT allowing the exchange for UIP from the CPU, which outputs the exchange enable signal to the input 22 of the device. This signal, synchronized by register 4, is a trigger condition for the element 10 AND-NOT allowing the exchange.

Thus, when an NAND element 10 is triggered, an exchange receipt signal is sent from the device CPU to the exchange resolution 28 to allow the exchange to signal that the CPU has provided its memory and its address, data, and control signals for the UIP. At the same time, the low level signal from the output of the exchange permission element AND –– HE transfers the bus drivers 2.1-2.P block 2, groups of 3 bus address formers and bus converters 7 and 8 sign write to the active state for transmitting the corresponding signals from their inputs to exits.

Element 11 AND-NOT records is intended to transfer groups 1. (N + 1) -1.2p bus drivers from UIP to active state for transmitting information from UHV 14 information highway to

information highways 13.1-13.p of group 13 in the presence of a high level of signals at the input 18 of the interprocessor exchange feature and at the input 16 of the device recording microoperation.

Element 12 is NOT intended to form a signal of one of the conditions of readout decoder 6 in the absence of a write micro-operation signal at input 16 of the device, and vice versa to prohibit read-through decoder 6 operation in recording modes from UIP in CPU memory when it arrives at device 16 for recording microoperations from pvv.

The PVV information line 14 is intended to be connected to the PVV information inputs-outputs, the PVV address highway 15 is intended to be connected to the PVV address outputs that address its memory, the device inputs 16-20 are the PVV outputs formed by its control device (corresponding to AHB), and the outputs 28 and 29 of the device are the AHB inputs (inputs of the logic conditions of the UHF control unit).

Information highways 13.1-13.ri of group 13 of CPU bus formers are designed to connect to the informational highway of the CPU, the address highway 23 of the CPU of the device is intended for connection to the same trunk of the CPU, inputs 21 and 22 of the request and authorization of the exchange from the CPU of the device are connected to the outputs of the CPU. The outputs 24.1-24.p of the group 24 of the output signals of the device record, the outputs 25 and 26 of the record attribute and the device access signal are used to connect to the CPU signal circuits of the same name. The output 27 of the exchange request from the UIP device serves to issue a signal to the CPU.

Blocks 30.1-30.p RAM memory are designed to receive (from the outputs of groups 32.1-32.p bus formers), store and issue (at the inputs of groups 33.1- 33.p bus formers) information under the control of signals and write signals from the corresponding addresses.

Element31 AND-NOT provides information transfer from blocks in 30.1-30.p of memory to group 13 of information highways (respectively to information highways m 13.1-13.p) through groups 33.1-33. bus drivers with a signal (low level) the inversion at the inverted output of the bus inverter 37 for the CPU (or at the output 26 of the device inversion signal) and the absence of a signal (low level) at the inverted output of the bus driver 39 for the CPU write attribute (or at the output 25 for the record of the device).

Group 32.1-32.p (33.1-33.p) bus drivers are designed to transfer information from group 13 or 41 CPU information highways (from the outputs of memory blocks 30.1-30.) To the information inputs of blocks 30.1-30.p. ti CPU (per group of 13 or 41 information highways of the CPU).

The group 34 of address bus drivers from the CPU is intended for issuing address addresses codes generated by the CPU to the address inputs of blocks 30.1-ЗО.п of memory.

Bus conditioners 35.1-35.p. of the block 35 of the write CPU bus formformers are designed to transmit recording signals from the CPU to its memory blocks 30.1-30.p.

Reverse bus driver 37 (39) (write attribute) The CPU is designed to transmit with inverting the signal from input 45 (44) a reference (write flag) to the CPU at the reversal input of blocks 3 30.1-30.0 memory and the inverse input of the 31 AND-NOT element (to the inverted control inputs of groups 32.1–32. bus drivers and direct input of element 31 NAND.

Group 36.1-36.p of resistors is designed to form reliable single signals on buses 24.1-24.p of group 24 outputs of the device recording signals while simultaneously remaining in the third state of outputs of bus drivers 2.1-2.P groups 2 and bus drivers 35.1-35. n group 35.

The resistor 38 (40) is designed to form a reliable single signal at the output 26 (25) of the inversion signal (recording attribute) of the device while being in the third with the output state of the bus driver 37 (39) inversion (recording indication) of the CPU.

At the same time, the outputs of tire formers 2.1-2.P and 35.1-35.p, 7 and 37, 8 and 39, as well as groups of tire formers 3 and 34, 1. (n + 1) -1.2p and 33.1-33.p cannot simultaneously be in the active state, i.e. when the outputs of one of these bus drivers are in the active state, the others are in the third state.

The conditions for converting the outputs of the respective bus driver devices to the third state are described above, while translating the bus drivers 35.1-35.p of block 35, bus drivers for inversion 37 and 39 for the CPU write attribute, and group 34 of address bus drivers for CPUs is produced by applying a single signal to

RAM access control input 46.

The PVV RAM unit 47 receives information from the PVV information highway 14, stores information and issues information on the same highway 14 under the control of the circulation and recording signals at the inversion inputs 40 and the PVV recording 49 at the addresses supplied to the address inputs of the 47 memory from address line 15 PVV.

We describe the operation of devices in general. In this case, we consider three modes of operation of the device.

A. Independent operation of processors, in which there is no influence of one processor on the operation of another.

In this mode, the signals at the inputs 16-19, 21 and 22 are missing, and the input 20

the devices are continuously supplied with sync signals from the UIP. At the same time, the output groups of the group of bus formers 1.1-1.2p from the CPU and PVV, the group 3 of bus formers, the addresses and the outputs of the bus formers 2.1-2.P, 7 and 8 are transferred to the third (high-impedance) state, which ensures the discontinuity of the address main 15 PVV from address line 23 CPU and information line 14 UIP from group 13

information highways 13.1-13.p CPU, which actually excludes the influence of the work of one processor on the work of another.

B. Mode of information exchange between

processors on the initiative of PVV.

This mode of operation of the device begins by applying the UHV signals to the inputs 18 and 19 of the device, and at the output 27 of the device a request signal is generated.

The CPU for the exchange, and the elements 10 and 11 of the NAND and the decoder 6 are prepared to operate on one of the inputs.

When the CPU is ready to exchange (for example, the completion of the next command), it outputs a signal to the device input 22, which is associated with the time grid of the UIP on register 4. Thus, the signal from output Q2 of register 4 triggers element 10 AND-NOT. output signal

which, arriving at the output of the device 28, informs the PWV about the readiness of the CPU for the exchange and, arriving at the control inputs of group 3 of the bus address formers and bus formers 2.1-2.p., 7 and 8, translates them

conclusions from the third to active state, i.e. allows the transmission of signals from the inputs to the outputs of these bus drivers (with or without inversion). After this, the PVV removes the signal from the input 19 of the device and exchanges between the memory of the PVV and the CPU, forming the corresponding addresses of these memories on the address highway 15 of the PVV and the access signals at the input 17 of the device when transmitting information from the CPU to the PVV or recording and access signals at the inputs 16 and 17 of the device when transmitting information from the PVV to the CPU. In the first case, the signal from the corresponding output of the decoder 6 translates to the active state the output of the corresponding group 1.1 (i 1, p) bus drivers, and in the second, the output from element 11 AND-NOT translates the active state to the outputs of group 1. (n + 1) -1.2p bus drivers.

In this case, the address and address signals are output to the device outputs 26 and 23 in both cases, and the recording and recording signal signals are transmitted to one of the outputs 24.i (i 1, n) and the device output 25 only in the second case, which ensures transmission information from the corresponding memory block CPU b of the informational line 13.i (i bm) of the CPU) to the memory block of the PVV (to the information highway 14 PVV) in the first case and in the opposite direction in the second case.

At the same time, the proposed structure of the device for interfacing two processors allows interfacing PVV and CPU having the following three features of their implementation. First, with the same amount of memory and CPU and UIP and tight correlation of their addresses and memory contents to these addresses, during the exchange of UIP, a single address is created on bus 15, which is used to read and write both from CPU and UIP and vice versa).

Secondly, with different volumes of memory of processors and the absence of mutual correlation of their content and thickness of the memory blocks (blocks 30.i (i 1, n) and 47, shown in Figures 2 and 3 for example) of the address registers during one exchange cycle (exchange of one word of the bus 14 format), the address on bus 15 is generated twice (once for block 30.i and the second for block 47 in the first of the mentioned cases of information transfer, and vice versa once for block 47, and the second for block 30.i in the second case of information transfer), and information from the memory blocks of the CPU and UIP is transmitted without storing in the register-latches of the bus controller of the corresponding memory.

Thirdly, with different volumes of PVV and CPU memory and the absence of address registers in their blocks, the address, as in the previous case on bus 15, forms the PVV twice, similarly to that described above, but when transmitting information from CPU memory blocks to the memory block The PVV, or vice versa transmission, is accompanied by the memorization of the transmitted information in the controller of the PVV memory busses.

Thus, the proposed device allows the processors to be interfaced with various exchange disciplines implemented by their memories.

B. The mode of information exchange between processors initiated by the CPU is as follows.

0 The CPU provides a signal to input 21 of the device, which is tied to the clock grid of which the UIP is made on register 4. This signal from output Q1 of register 4 is transmitted to output 29 of the device and is fed

5 signal exchange requirements (or interrupts) in UIP.

Further information exchange is performed by the UIP as described above, and all exchange instructions can be specified in

0 fixed CPU memory locations (mailbox). Reading and other instructions UIP performs in the second mode of operation described above (B).

Claims (1)

Invention Formula 5 A device for interfacing two processors, comprising a bus reference driver and an AND element, the exchange request input from the device I / O processor being the first input of the AND element, the output of which is the exchange request output from the device I / O processor differing in that, in order to increase the exchange performance, it additionally contains a block 5 of the n bidirectional groups of bus drivers, a group of bus address drivers, a synchronization register, a block of bus drivers, a write decoder, a read decoder, a bus driver of the write feature, an AND-NOT element of the exchange, an AND-NOT element, and an NOT element, In this case, the high-order bits of the address output of the I / O processor are the input of a device for connecting to the inputs of a group of bus address drivers, the outputs of which form the output of the device for connection to the address input of a central a processor, inputs and Request razreshe0 audio exchange from the central processor unit are connected respectively to the first and second data inputs of the synchronization register microoperation input device connected to the recording 5 the first control input of the write decoder, the input of the element NOT, the information input of the bus driver of the recording feature and the first input of the recording element IS NOT the output of the element is NOT connected to the first control input of the read decoder generated by the clock output of the I / O processor , connected to the synchronous register synchronization register and the second control input of the write decoder, the input of the interprocessor exchange feature of the device is connected to the second control input of the decoder and the readings and the second inputs of the AND element and the NAND recording element, the first output of the synchronization register are the exchange request output from the central processor of the device, the second output of the synchronization register is connected to the first input of the NAND element of the exchange resolution, the output of the AND element is connected to the second the input of the exchange resolution NAND element, whose output is the output of the exchange resolution from the central processor of the device and connected to the inverse control inputs of the bus recorders of the group record, bus drivers the address and the sign of the record and the group address bus drivers, the inverter outputs of the write decoder are connected to the information inputs of the bus recorders group recording, the outputs of the bus recorders group recording are the outputs of the recording signals of the group of output signals of the device recording, the input micro-operation of the device address inverter and the third control inputs of the write and read decoders, the lower bits of the address output of the I / O processor are device inputs for connecting to the groups of information inputs of write and read decoders, inverted outputs of bus formers of inversion and write attribute form the outputs of the signal of inversion and sign of recording of the device, respectively, invert outputs of the decoder of readout from the first to nth are connected to inverse control inputs of the groups of bus formers the first to the n-th block of bidirectional groups of bus drivers, inverse control inputs of the groups of bus drivers from (n + 1) to 2 n-th of the same block with dineny yield NAND recording data inputs i-th group (1 i n) of bus formers of the block of bidirectional bus formers are connected to the outputs of the (IJ) group of bus formers of the same block and form the information input-output device to connect to the information input-output of the central processor, the outputs of the i-th group of bus drivers for the block of bidirectional groups of bus drivers are connected to the information inputs of the (n-n) -th group of bus drivers of the same block and form the information input-output of the device for connection to the information input-output processor I / O.