SU1689961A1 - Device for information exchanging between computer and peripherals - Google Patents

Abstract

The invention relates to computing and can be used on computing systems for building interfaces to interface DVMs with remote external devices. The aim of the invention is to simplify the interface of the interface. To this end, the device containing the control word register, the address selector and the address generation unit, has entered the first and second information input registers, the first and second information output registers, the input synchronization unit, the output synchronization unit, the address switch and the input / output control unit . 1 hp ff, 1 tab., 10 ill.

Description

cl

with

The invention relates to computer technology and can be used in computer systems for building interfaces for interface between digital computers and remote external devices.

The purpose of the invention is to simplify the interface of the interface.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a block diagram of output synchronization; in fig. 3 is an address selector diagram; in fig. 4 is a block I / O control block diagram; in fig. 5 is a block diagram of input synchronization; in fig. 6 is a diagram of an address generation unit; in fig.

7- control word structure; in fig.

8- time diagram of the operation of the output synchronization unit; in fig. 9 is a time diagram of the device operation in the mode of information transfer from the digital computer to the internal control unit; in fig. 10 - time diagram of the device

in the mode of information transfer from VU to digital computers.

The device for changing information between the digital computer and external devices contains the first information output register 1, the control word register 2, the first information input register 3, the output synchronization unit 4, the input synchronization unit 5, the second information output register 6, the second information input register 7, an I / O control unit 8, an address selector 9, an address switch 10, an address generation unit 11.

The device also has a reset bus 12, a 13-pin bus, a code bus for the output of 14 CVMs, a bus 15 and 16 signs of output operations, a code bus for the input of the CVM bus 18 and 19, a control word and information read bus, bus 20-22 tires 23 information digital computers, tires 24 information VU, tires

ON 00 O NO

with

25 and 26 of synchronization of digital computers, control word sign 27 (BUS), bus 28–30 of the clock synchronization, bus 31 of readiness, write bus 32, gate bus 33, bus 34–36 of synchronous information bytes of the CVM, bus 37 of strobe information WU, code bus 38 output WU, code bus 39 input WU, tire 40 identification WU.

In this case, the registers 1-3, the output synchronization unit 4, the input synchronization unit 5 are included in the digital computer exchange device, and the registers 6 and 7, the control unit 8, the address selector 9, the address switch 10, the address generation unit 11 are an integral part controller slave.

Block 4 output synchronization (Fig. 2) contains four trigger 41-44, counter 45, two shift registers 46 and 47, pulse shaper 48, six AND 49- 54 elements, two IE55.56 elements, OR 57 element, 2I element- OR 58.

The address selector 9 (FIG. 3) contains a comparison circuit 59, two flip-flops 60 and 61, the AND element 62, and a pulse shaper 63.

The I / O control block 8 (FIG. 4) contains three triggers 64-66, three pulse makers 67-69, two elements OR 70, 71, seven elements AND 72-78, three elements NOT 79-81.

The table shows a list of interface buses and their purpose.

Block 5 (Fig. 5) input synchronization contains two trigger 82, 83, three formers 84-86 pulses, the element is NOT 87.

Block 11 (FIG. 6) of the formation of the address contains the register 88 and the decoder 89.

The operation of the device is described taking into account the use of a 24-bit digital computer.

The device works in two modes:

-the release of information from digital computers to external devices (WU),

- reception of information in digital computers from external devices.

The issuance of information from the digital computer in VU.

This mode is provided by sequential execution in the digital computer of two output commands (V1P, V2P). The timing diagram of the mode is shown in FIG. 8, 9.

The first command issues a control word (USL) defining the address of the VU group (device), the VU address in the group (in the instrument), a sign of the direction of exchange (I / O). A variant of the control word structure is shown in FIG. 7

This device does not specify the use of 1–4 bits of the 1st byte and the entire 3rd byte. Their purpose can be arbitrary, taking into account the exchange algorithms and timing diagrams of the device

The second command issues information from the digital computer to the address of the first command of the slave. Both output commands are accompanied by issuing corresponding characteristics from the digital computer - PV1P via bus 16 and PV2P via bus 15. The control word and information are issued via bus 14. The falling edge of the PV1P sign 24-bit control word issued from the DVR is written into the register

0 2. At the same time, this sign is fixed by the trigger 41, and through the elements NOT 55 and OR 57 the G is written to the first digit of the register 46 and the code 0 ... 0 to the register 47 (see Fig. 2).

5 In flip-flop 42, the output signal of flip-flop 41 is synchronized (linked) to the positive edge of the clock pulse outputted from the digital computer via bus 13. At the output of flip-flop 42, a control word (POSL) is generated.

The information returned from the digital computer via the tires 14 by the falling edge of the PV2P flag is recorded in register 1. And the sign itself is recorded by the trigger 43. At the same time

The 5 1 and the fifth bit of the USP front edge is taken to trigger 82, and the rear edge is rewritten to trigger 83, forming a constant Ready signal on bus 31.

0 The output signal of the trigger 42 allows the arrival of clock pulses on the bus 13 through element 2I-OR 58 to the input of a one-bit counter 45, from the output of which the shift pulses go to the C input

5 (shift input) of register 46, and the inverse values of these pulses are at the C input of register 47. The three first read signals from the output signals of register 46 on the elements 49-51 produce three read signals

0 Read 1 USL, CAL.2 USL, CUR. 3 CONV. which, via buses 18, arrive at the input of register 2. These signals alternately transfer three bytes of the control word over the tires 23 Inf. Digital computer in

5 external devices. At the same time, two signals are generated at the outputs of register 47.

Sync Sync.1 TsVM, Sync.2

Digital computers transmitted by tires 25, 26 during

external devices as control word synchronization signals,

The fourth shift produces a signal at the fourth output of the register 47. This signal sets the one state of the trigger 44, to zero

The 5th state of the flip-flop 42, completing the formation of the START signal, and the counter 45 is reset via the shaper 48 to the zero state. The leading edge of the output signal from the flip-flop 44 through the OR 57 element is provided to write to registers 46, 47

codes OOOG, 0 ... 0, respectively. The clock signals entering through the 2I-OR 58 element are started in the counting mode by the counter 45, the output pulses of which shift the registers 46, 47. From the output signals of the register 46, three read signals from the register 1 three bytes of information are generated from the output signals of the register 46 provides their transfer to tires 23 Inf. Digital computers to external devices. At the same time, at the outputs of register 47, two synchronization signals of these bytes of information are generated, transmitted via buses 25.26 to the slave where they receive these information bytes. The falling edge of the signal Counting. Inf (one of the buses 19) is set to the zero state by a trigger 43, and then the signal from the fourth output of the register 47 is set to the zero state by the trigger 44. This completes the operation of the equipment of the DVR exchange device and returns to its original state condition.

The operation of the slave controller begins with the reception of the control word from the SA. The control word from the output of register 2 is fed to the input of the comparison circuit 59 gated by the control word sign PUSL on bus 27. When comparing the code of the VU group number (bits 6-8 USD) with the leading edge of the Sync signal on the 10 address switch VU .1 the digital computer on bus 25 sets trigger one 60 to one state. At the same time, this front of a unit of the fifth digit USL is detected by trigger 64, trigger 64. The second leading edge of the signal formed on trigger 61 is taken through element 62 into register 88 Ayt Usl (address of the VA in the group). The output potential of the trigger 64 allows the generation of synchronization signals on the elements 74, 75 and NOT 79, which ensure the reception of three bytes of information arriving on the buses 23 in the register 7.

On the driver 67, from the back of the signal on bus 36, a signal is generated which, via element 70, travels via bus 33 to the gate input of the decoder 89. At one of the outputs of the decoder 89, a signal is generated that corresponds to the address code in register 88. This signal is used to input in the 24-bit code of the information received in register 7.

Reception of information in the digital computer from VU.

This mode is provided by sequential execution in the digital computer of two output commands (V1P, V2P) and input commands (GDP). The timing diagram of the mode is shown in FIG. 8, 10. The first command from the digital computer issues a 24-bit control word

(US), which, at the trailing edge of the PV1P flag, is written into control word register 2. At the same time, this sign is fixed by the trigger 41, and through the elements NOT 55 and OR 57 T is written to the first digit of the register 46 and the code 0 ... 0 to the register 47 (see FIG. 2). On the trigger 42, the output signal of the trigger 41 is synchronized (linked) to the positive edge of the clock pulse output from the digital computer via the bus 13. At the output of the trigger 42, a control word (PUSL) is generated,

In the team (32P) from the digital computer to

5, the information bus is given a code 0 ... 0, an Ego command in this mode serves as a control for generating synchronization signals for the controller of an external device. The sign of the PV2P is fixed by the trigger 43 and at the same time by the second bit of the USL the leading edge of the sign of the PV2P is received in the trigger 82. and the rear one is rewritten in the trigger 83, removed after the completion of the VP2 command

5 Readiness from the input of the digital computer (in chic 31). In this case, the next command (VVP) is delayed in the digital computer until the Ready signal is restored at the digital signal input.

0 Formation of readout signals on buses 18, 19, synchronization signals on buses 25, 26 and transmission of control word and information byte to the slave is similar to the output mode

5 information from digital computers. In this case, the register 7 records the code 0 ... 0.

The control word from the output of the register 2 is fed to the input of the comparison circuit 59 gated by the sign of the control

0 words PUSL on bus 27. When comparing the code of the VU group number (bits 6-8 USD) with the front of the signal preset on the 10 switch of the VU address, the sync1 of the digital computer on the bus 25 is set to one trigger 60. At the same time, this front is zero The second bit of the USL through the elements is NOT 80, and 73 is fixed by the trigger 65. The leading edge of the signal formed on the trigger

0 61. through the element 62 and into the register 88 the second byte of the control word is received. The output potential of the trigger 65 is allowed to form on the element And 73, the driver 69 and the element 70 of the building block decoder 89. At the same time, a signal is generated at one of its outputs that corresponds to the address code in the register 88 and serves as a sign of the request for a VU to issue information. From WU busses 38 receives information recorded in the register b by the synchronization signal on the bus 37.

The output potential of the trigger 65 of the Signiopo Siihr 1 DVM. Sync.2 CVMs arriving in V2P operations (no POSL sign), elements 76, 77 and trigger 66 generate signals for reading information bytes from register 6. At the same time, signals Sync.1 WU, Sync.2 WU on buses 28, 29 are received on the block of synchronization block 5 in the code, the byte synchronization signals of the WU information,

The falling edge of the signal of Sync.2 WU through the driver 68 and the element OR 71 is reset to the zero state trigger 65, thereby driving the equipment of the WU controller to its initial state.

And :) the signals of Sync.1 WU, Sync.2 WU on the element HE 87 and shaper 84-86 form the reception of individual bytes of information WU in the register 3. The synchronization signal of the third byte from the output of shaper 86 sets the bullet state triggers 82 83, forming the Ready signal 1 on bus 31, which is fed to the input of the digital computer. After that, the digital computer executes the command of the register (VaP) register 3. This completes the considered one. device operation mode.

Claims (2)

Invention Formula 1, A device for information exchange between a digital computer and anonymous devices, containing a control word register, an address selector — an address generation unit whose information output is an output of a device for connecting an external device to the address input, information outputs of the control word register from first to last the third is connected to the first information input of the address selector and the information input of the address generation unit; the information input of the control register is the device input for connecting The information output of the digital computer and the first output of the address selector are connected to the input of the record of the address generation unit, characterized in that, in order to simplify the interface, the first and second information input registers are entered into it, the first and second information output registers input, output synchronization unit, address switch and input-output control unit, with the information input of the first information output register connected to the device input for connecting to the information output of a digital computer, information translational pen come out of register information output from the first through third obedine- control word register outputs and are connected to the same information inputs of the second information input register; one of the bits of the first information word of the control word register is connected to the first input enable input of the I / O control unit, the first output of the output synchronization block, and these rotation of the control word register is combined and form the input of the device for connecting to the first output of the sign of the DVM operation, with the start input of the output synchronization block, the digital input The first information output register and the first clock input of the input synchronization block are combined and form the device input for connecting to the second output of the digital computer operation sign, the input clock input trigger input is combined with the information from the information input bits of the first information output register, the enable input of which is connected. to the first output of the output synchronization block, 5 the second output of which is connected to the control word register input enable input, the output synchronization unit clock input is the device input for connecting to the clock output, the digital computer output, the third output output unit output terminal is connected to the address selector sync input and the first input / output control sync input , the fourth output of the output synchronization block is connected to the input 5 of the initial setting of the address selector and the second synchronous input of the I / O control unit, the fifth output of the output synchronization unit is connected to the address enable input of the address selector and the input 0 indications of the operation of the I / O control unit, the second output of the address selector is connected to the second input enable input of the I / O control unit, the outputs from the first to the third of which 5 are connected to the synchronous inputs of the second input data register of the same name, the fourth and fifth outputs of the I / O control unit are connected respectively to the input of the initial installation and the input 0 permitting the reception of the address generation unit, the information output of the second information input register is the output of the device for connecting to the information input of an external device, the enable inputs of the second register of information output from the first to the third are connected to the outputs of the vodom-zaod control unit from the sixth to the eighth, In addition, the sixth and seventh outputs of the I / O control unit are connected respectively to the second clock input and the input to the input synchronization block, the information input and the sync The second output register register is the input of the device for connecting respectively the information output and the output synchronization output of the external device, the information output of the second information output register is connected to the information inputs of the first to the third first information input register, the output of which is the output of the device connection to the information input of the digital computer, the second information input of the address selector is connected to the output of the address switch, the clock inputs of the first register The information from the first to the third is connected to the outputs of the input synchronization block from the first to the third, the fourth output of which is the output of the device for connection to the readiness input of the digital computer. 2. A device according to claim 1, wherein the I / O control unit contains three triggers, three pulse makers, two OR elements, seven AND elements and three NOT elements, the first the block enable input input is connected to the first input of the first element I and through the second element NOT to the first input of the second element I, the first synchronized input of the block is connected to the second inputs of the first and second elements I, the first inputs of the third, fifth, sixth elements And to the synchronous input of the third trigger, the second synchronized input of the block is connected to the first input of the fourth AND gate, a reset input The third trigger and the first input of the seventh element I, the second input of the block reception permission is connected to the third inputs of the first and second elements I, the input of the operation indicator of the block is connected to the second input of the seventh element I, and through the third element NOT to the second inputs of the third, fourth, n This and the sixth elements I. The output of the first trigger is connected to the third inputs of the third and fourth elements, the output of the third element and is connected to the first output of the unit, via the first element NOT to its second output, the output of the fourth element. Connected to the third output of the block, and through the first pulse shaper connected to the first inputs of the first and second OR elements, the output of the second trigger connected to the third inputs of the fifth, sixth, seventh AND elements and the third input of the third trigger, the fifth output of the And second element the output of the block, the output of the sixth element And is connected to the sixth output of the block and through the second pulse shaper connected to the second input of the second element And, the output of which is connected to the reset inputs of the first and second triggers and The fourth output of the block, the outputs of the first and second elements I are connected to the synchronous inputs of the first and second triggers respectively, the output of the third trigger is the eighth output of the block, the output of the seventh element I through the third pulse generator connected to the second input of the first element OR the unit output, and the information inputs of the first and second triggers are connected to the unit potential bus. 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