SU1300544A1 - Device for displaying information on screen of cathode-ray tube (crt) - Google Patents

Abstract

The invention relates to computing and can be used in display devices in cases where precise movement of the image on the CRT screen in the horizontal direction is required. The purpose of the invention is to expand the field of application of the device by improving the dynamic characteristics of the displayed information by moving the image with a discrete element of the image - achieved by entering the register 3 offset address, the counter 4 offset pulses, and the driver 11 of the delay pulse. corresponding functional st. Zey 2 ZP f-ly, 3 Il. W (L with

Description

The invention relates to computing technology and can be used in devices for display in cases where precise movement of an image on a CRT screen in the horizontal direction is required.

The purpose of the invention is to expand the field of application of the device by improving the dynamic characteristics of the displayed information by moving the image with discrete one image element.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a functional diagram of the delay pulse former; in fig. 3 is a control block diagram.

The device contains a synchronizer 1, a starting address register 2, an offset address register 3, an address counter 4, a memory block 5, a shift register 6, a video signal generator 7 a cathode-ray tube 8 (CRT), a control block 9, a bias pulse counter 10, a driver 11 pulse delay.

Positions 12-14 denote the first, second, and third inputs of the device.

Positions 15–18 are the second, third, fourth, and first outputs of the synchronization unit 1, respectively.

Positions 19–23 from the first to the fifth outputs of block 9.

The positions 24 and 25 are the outputs of the correspondingly control factor I1 of the counter 10.

Shaper I1 pulse delay contains the first trigger 26, the swarm trigger 27, the element 28 And the element 29 of the delay.

The control unit 9 contains an annular shift register 30, executed on the flip-flops 31, 31g, SZ, SZ And 32 - 36 elements and flip-flop 37. The shunt's circular register 30 and flip-flop 37 form the address counting signal, the And element 33 is the write signal to the counter 4 , the element 34 And the counting signal of the address, the element 35 And the signal recording to the shift register 6, the element 36 And the control signal of the memory block 5.

The bit size of register 30, register 3, register 6 and counter 10 depends on the size of memory block 5

For definiteness, the memory block size 5 is taken equal to eight

In this case, the register size 30 must be equal to four, register 6–8, register 3 - three, and counter 10 - three.

The horizontal sync signal is designed to control the delay pulse generator 11 and the counter 10 and can be formed, for example, by using a counter and

trigger (not shown).

The location and duration of the pulses are shown in FIG. 4-6.

The device works as follows.

In the case of power-up, a control computer (not shown) generates a reset signal at input 14, which resets registers 2 and 3.

For this reason, an initial installation cycle is formed, which involves binding the pulses of the control unit 9 to the phase synchronization signal, taking into account the state of the register. 3.

The data from register 3 is written to counter 10 by a low level horizontal sync signal, which simultaneously disables the operation of counter 10 in counting mode. The high level of this signal allows the counting of clock pulses to the counter 10 | working on the subtraction. A low-to-high horizontal sync signal difference sets trigger 26. As the counter, 10 is in the zero state, the first low-clock pulse after the horizontal low-sync signal from low to high forms a transfer signal at output 25, which confirms trigger state 27; when ring shift register 30 is 0000, a prize signal is generated that cocks trigger 27. The brake signal from output 24 is fed to the reset input of shift register 30, holding it in SRI 0000 signap This also resets the flip-flop

26. The duration of the deceleration signal depends on the phase of the anchor signal with respect to (cnap / line sync.

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The signal at the output 24 ends when a second signal appears at the output 25 (transfer).

The phase of the signal at output 25 depends on the phase sync signal and the state of register 3. In this case, register 3 is cleared, the initial setup cycle determines the phases of the signals at the outputs of control unit 9 relative to the horizontal sync signal. Simultaneously with the appearance of the next horizontal synchronization signal, an anchoring signal appears; however, these signals do not change the state of trigger 27, because the delay of delay element 29 is greater than the delay of element 28 I. The next interlocking signal sets trigger 27, but the transfer signal at output 25 resets this trigger, while the duration of the inhibitory signal at output 24 is less period of the clock pulses, so in this case the deceleration signal does not change the phases of the signals at the output of the control unit 9. A braking signal of this duration is generated before the information in register 3 is changed.

Simultaneously with the termination of the horizontal synchronization signal, an address control signal is generated at the output 16. The high level of this signal and the low level of the signal permitting the formation of a video signal using element 33 form the signal at output 19, which overwrites the data from register 2 to counter 4. The contents of counter 4 determine the address of memory block 5, from which The swarm reads the data. The signal at output 22 writes the data read from memory block 5 to shift register 6. The clock pulses at the output 18 shift the data in the register 6 shift. From the output of this register, data in the form of a sequential code is fed to a video signal shaper 7, which, at a high signal level at output 15, transmits data in the form of a video signal to a control electrode of a CRT. The video signal is generated in the cycles described above. The duration of the cycles depends on the size of the memory block 5 and its speed.

To move the image to register 2, and register 3 write a number indicating how many elements of the decomposition to the left the image should be shifted. The lower order bits are recorded in register 3, and the older ones in register 2.

Register 2 defines the initial state of the address 4 counter and thus the first address of the memory block 5 from which data will be read. Since it has changed. the contents of register 3 and counter 10 change the phase of the transfer signal at output 25, and a data movement cycle is performed which differs from the initial setting only the data different from O in register 3.

In this case, the contents of counter 10 by the time of counting by the horizontal synchronization signal are different from zero, and the transfer signal at the output 25, resetting the trigger 27, will be delayed in phase relative to the transfer signal generated in the zero state of the counter 10 by time T, proportional to the number recorded in counter 10 and register 3

where K is a number in register B;

t - the period of the next clock

pulses at the output 2 of the synchronizer 1.

As a result, an increase in one of the cycles generated by the control unit 9 occurs.

If the number of states that can take register 2 and, respectively, counter 4, is equal to the number of cycles of access to memory block 5 for the period of the horizontal synchronization signal, then when the image is shifted to the right, the last positions of the line are displayed in the first line positions no shift. In this case, to shift to the right, it is necessary to write down the number determined from the expressions in the 1st register;

 - And,

where N is the number of display elements by which the image must be shifted to the right (without taking the sign into account).

After the scrolling cycle, in all subsequent cycles (before the new data is written to register 3), the deceleration signal at output 24 is formed by a duration that does not change the phase of the signals at the outputs of control unit 9.

Thus, the position of the image on the CRT 8 screen with an accuracy of one display element is determined by the data written to the registers.

The device is asynchronous with respect to the computer, since the arrival time of the recording signals at input 13 and the reset at input 14 is not critical with respect to the horizontal synchronization signal. If by the time this signal falls in the register 3 and, accordingly, in the counter 10, the sufficient data is not recorded, the image is disturbed in one line of decomposition, which practically does not reflect on the image quality.

Claims (3)

Invention Formula one . A device for displaying information on a cathode-ray tube (CRT) screen, containing a starting address register, whose information input and recording and reset inputs are the first, second and third inputs of the device, and the output connected: to the information input of the address counter, input the control of which is connected to the first output of the control unit; the counting input is connected to the second output of the control unit; the output of the address counter is connected to the information input of the memory block whose control input is connected to The other output of the control unit, the output of the memory unit is connected to the information input of the register, the shift, the control input of which is connected to the fourth output of the control unit, the clock input to the first output of the synchronizer, connected to the clock input of the control unit, the output of the shift register is connected to the information input of the video signal generator, the control input of which is connected to the second output of the synchronizer connected to the recording control input of the control unit, the control input address of the control unit is connected to The output of the synchronizer is about the fact that, in order to expand the field of application of the device by improving the dynamic characteristics of the displayed information by moving the image with a discrete single picture element, it contains the offset address register, the information input and the recording inputs and reset. which are connected respectively with the first. the second and third inputs of the device are a pulse counter bias and a delay pulse shaper, the output of which is connected to the reset input of the control unit, the fifth output of which is connected to the input of the delay pulse shaper signal, the synchronous input of which is connected to the fourth synchronizer output connected to the bias pulse synchronizer input , the clock input of which is connected to the first output of the synchronizer, the output of the offset pulse counter is connected to the overflow input of the delay pulse shaper. 2. The device according to claim 1, wherein the control unit contains a ring shift register, the inputs of which are a clock input and a reset input of the block, the first output is the fifth output of the block and connected to the first inputs of the first element I and the trigger, the output of the first element I is connected to the first inputs of the second and third elements I, the second inputs of the first and second elements I are connected respectively to the output of the first bit of the ring shift register and the clock input of the block, the output of the second AND element is the fourth output of the block, the second inputs of the third element AND and the trigger are the control input of the block address, the third input of the third And element is the control input of the block, and its output is the first the output of the block, the trigger output is connected to the first input of the fourth element And, the inverse output of the last section of the ring shift register is connected to the first input of the fifth element And and the second input of the fourth element And, the third input of which and the second input of the fifth element And connected to the output of the corresponding bit The terminals of the ring shift register, the output of the fourth and fifth And elements are the second and third outputs of the block, respectively. 3. The device according to claim 1, about tl and - the fact that the delay pulse shaper contains the first trigger, the first input of which is /  go is the synchronizer of the imager, its output through the delay element is connected to the first input of the second trigger and directly with the first. the input of the element And, the second input of which is the input of the grab eqi signal, the output of the element And is connected to the second input of the second flip-flop, the third the input of which is the overflow input of the former, the output of the second trigger is the output of the former and is connected to the second input of the first trigger.