SU1499331A1 - Device for displaying symbol information on video monitor screen - Google Patents

Abstract

The invention relates to automation and computing and can be used to display information from a computer. The purpose of the invention is to simplify the device. This is achieved with the exception of the multiplexer and the introduction of the corresponding functional links. The device allows the display of symbolic and pseudographic information on the screen of a video monitoring unit. 1 il.

Description

The invention relates to automation and computing technology. And can be used to display information on short-circuit computers.

The purpose of the invention is to simplify the device.

The drawing shows a block diagram of the device.

The device contains a clock pulse generator 1, control block 2, memory block 3, character generator 4. Control block 2, single vibrators 5 and 6, first counter 7, first 11 and second decoders 8 and 9, second and third counters 10, and P. contains a fixed memory block 12 and a shift register 13.

Memory block 3 contains buffer 14 and memory block 15. Positions 16–18 denote the video input, the lower case sync input and the frame sync input of the video monitoring unit, respectively.

Positions 19-22 designate the ready output, the first and second control inputs, and the address inputs of the device, respectively.

The device generates a full television signal that can be supplied to the Video input of a standard video monitor unit or a TV, and provides the formation of alphanumeric and pseudo-graphic characters.

Each familiarity is displayed by a matrix of points of a television raster without intermediate obscuring. The device allows displaying the 32nd lines of 64 characters each, which corresponds to the standard adopted in most simple micro-computers. The device uses the principle of continuous combining and reproducing the contents of memory block 3 on the screen of the video monitor. Memory block 3 is part of the microcomputer memory.

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Information is recorded and read from it by the software implementation function of the display.

The clock generator 1 generates clock pulses with a period equal to the time of exposure of one point. The pulses go to the shift register 13 of the character generator 4 and the counting input of the third counter 11, made on the chip 155IE; 8o From the output P of this counter, the pulses are continuously following the frequency where the frequency is following clock pulses, are fed to the input of the first counter 7 Perv decoder 8 analyzes the state of the counter

7and generates line sync pulse (FID). The structure of the decoder 8 determines the time parameters of the FID C of the Y output of the counter 11 pulses, which follow at a frequency of 1/8 FTOk.-r (the division factor for the output Y is given by a combination of logic levels at inputs Y1-Y32), clocks the second counter 10, which produces over the outputs 2 ° —2, recalculation of the input pulses into coefficients determined by the frame format, ensuring the addressing of any cell of the memory block 15. The address from outputs 2 ° - 2 unambiguously determines the position of the symbol on the screen horizontally, and from outputs 2 ° - vertically. The memory block 12 of the symbol generator-4 carries out a scan of the character code arriving at its address inputs from the output of memory block 15 into the character matrix by successively addressing the rows of the character matrix with the output address 2 ° - 2 of counter 8. Register 13 of character generator 4 There is no transformation, parallel format of the row of the matrix of the character to the serial - with the frequency FTQICT

When counter 7 reaches code 8 (64 familiarity is counted, a line blocking pulse starts), decoder 18 at the output of HL produces a blanking pulse, which is fed to input T of the third counter 11 and prohibits the arrival of pulses 1/8, from output Y. Register 13 and counter 10 are not clocked and prepared to display the next line of the television raster. When the counter reaches 7, code 11 (the beginning of the next TV line) the decoder

8 output D3 generates a pulse, resetting counter 7 prepares it to display the next line. After displaying the last familiarity of the last line, a frame blanking pulse begins on the screen. Output 2 of counter 10 shows a logical unit signal that triggers the single vibrators 5 and 6 and enters input A7 the second decoder 9 and the input A3 of the first decoder 8 For the duration of the personnel blanking pulse decoder 8 output DO produces a blanking pulse, prohibiting clocking counts Fig. 10 and the shift register 13. The time parameters of the single-oscillators 5 and 6 determine blanking and synchronizing (frame pulses, respectively. The pulse from the output of the one-vibrator 5 allows the decoder 8 to reset the counters 7 and 8, preparing the device for displaying the next frame.

During the frame blanking pulse, the counter 10 is not clocked and access to memory block 3 is allowed. Addresses from the address bus go to a group of inputs DO-D5, D9-DI3, counter 10, controlled by a signal to access memory block 3 from the decoder DO output 9 Data on the data bus through buffer 14 is fed to inputs DO-D7 of memory block 15 Data transfer direction is determined by the signal from the output D1 of the decoder 9 ,, The structure of the decoder 9 is such that the signal at the DO output appears when the AO- A4 signals from the higher address bus bits that determine the area of memory block 3 in the address space of the microcomputer, at the input A5 or A6 of the read or write signals, respectively, and at the input A7 of the personnel slug pulse from the output 2 of counter 10, the signal at the output Dl corresponds to a logical zero (write) during the write cycle in the block 15, a signal at output D2 appears when accessing memory block 3 during the regeneration of the image on the screen of the video monitoring unit.

Thus, the exchange of information between the computer and the memory block 3 is possible only during the period of the reverse sweep of the frame scan of the video monitor block, when the counter 10 does not work in | mode. accounts. If the reversal occurs during the forward stroke (during image regeneration), then the sixth output of the device (output D2 of the decoder 9) will produce a logical zero signal, which will delay the reversal until the appearance of a personnel blanking pulse.

This prevents the appearance of an instantaneous erroneous display on the WKB screen, and a slight decrease in the performance of the computer is permissible, since it occurs only during the exchange of information with the memory unit 3.

Thus, the exception from the known device multiplexer and the introduction of the corresponding functional | - connections allowed to simplify the proposed device

Claims (1)

Invention Formula A device for displaying symbolic information on the screen of a video monitoring unit, containing a memory unit, character generator, control unit, clock generator, the output of which is connected to the clock inputs of the control unit and character generator, the control input of which . - 499331 connected to the first output of the control unit, the outputs of the first group of which are connected to the address inputs of the first group of the character generator, the address inputs of the second group of which are connected to the outputs of the group of the memory block, information inputs and outputs of which are informational The device's JO I / O, write and read control inputs are connected to the second and third outputs of the control unit, the fourth and fifth outputs, respectively. 15 which are connected respectively to the horizontal and vertical sync inputs of the video monitoring unit, the video input of which is connected to the output of the character generator, the sixth output of the control unit 20 is the output of the device’s ready signal, the first and second control inputs of the control unit are the first and second control inputs of the device I distinguish 25 so that, in order to simplify the device, the outputs of the second group of the control unit are connected to the address inputs of the memory block, the address inputs of the control unit are addressable in odes device. sh ША7 SHOD UlAJ SHA2 SHAZ WAti SHA5 Shab ShA1 WAS WAS Shayu SHAP ША15 to Reading 21 Record jg mos / r7 & "