SU1312557A1 - Information input device - Google Patents

Abstract

The invention relates to automation and computing and can be used to enter information over a two-wire communication channel. The purpose of the invention is to enhance the functionality by providing interface with a two-wire half-duplex communication channel. The goal is achieved in that a device containing a pulse generator, a keyboard and a register is entered into a interface block, a serial to parallel converter, a decoder, a parallel code to serial converter, a counter, an instruction register, a data buffer, a status word generator , control unit, switch. The formation of the updated status byte and the status byte with different indicators allows, in addition, to increase the reliability of information transmission over the communication channel. 11 il. i (/

Description

1 13

The invention is related to automation and computer technology and can be used to sequentially enter information over a two-wire half-duplex channel in with. The purpose of the invention is to enhance the functionality by providing interface with a half-duplex communication channel.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a diagram of the first code converter; in fig. 3 is a diagram of the second code converter; in fig. 4 is a diagram of the first counter; in fig. 5 - scheme of the second register; in fig. 6 is a data buffer diagram; in fig. 7 is a diagram of a condition word generator; FIG. 8 is a diagram of a control unit; figure 9 is a timing diagram of the operation of the pulse integrator; in fig. 10 and 11 are diagrams of operation of the first and second converters.

The device contains (Fig. 1) a pulse generator 1, a keyboard 2, a first register 3, a first converter 4 codes., A conjugator 5, a second converter 6 codes, a first counter 7, a second register 8, a data buffer 9, a word conditioner 10. The control unit 11, the switch 12, the decoder 13. The positions 14- 58 designate the inputs and outputs of the device units. Position 59 denotes the input / output device, position 60 - the input device.

The first Converter (Fig. 2) contains the Converter 61 parallel code to serial, node 62 convolution, the first 63, the second 6 and the third 65 elements I.

The second converter (fig. 3) contains the converter 66 of the serial code into the parallel one, the third register 67, the control unit 68, the first trigger 69, the second counter 70 the second decoder 71.

The first counter (Fig. 4) contains the fourth 72, the fifth 73, and the sixth 74 AND elements, the first OR element 75, the third counter 76, the third decoder 77. The second register (Fig. 5) contains the second 78 and the third 79 triggers.

 The data buffer (Fig. 6) contains the seventh 80, eighth 81, ninth 82 and tenth 83 elements And, the fourth 84, the fifth 85 and sixth 86 registers.

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The shaper of the state word (Fig. 7) contains the fourth .87 and n - thir 8B triggers, eleven 89 and twelfth 90 elements AND, sixth, 91 and seventh 92 triggers, second 93, third 94 elements, eighth trigger 95, thirteenth element And 96.

The control unit (Fig. 8) contains a group of elements AND 97-105, a fourth 106 and fifth 107 elements OR.

The generator 1 includes a pulse generator, the output of which is connected to a three-discharge counter with a decoder. The pulses produced by the counter are shown in the time diagram of FIG. 9 at positions 1- (3), 1- (4). The pulses produced by the decoder are shown in the timing diagram of FIG. 9 at positions 1- (6), 1- (7), 1- (9). The pulses shown in positions 1- (2) and 1- (5) differ only by a shift in time. The pulses produced at the output of generator 18, 1 are shown in the time diagram of FIG. 9, position 1- (4). The pulses produced at the output 16 of the generator 1 are shown in the time diagram of FIG. 9 at 1- (5), 1- (7), 1- (8) and 1- (9). The pulses produced at the output 17 of the generator 1 are shown in the timing diagram of FIG. 9 at the positions 1- (1), 1- (2) and 1- (5).

The decoder 13 has outputs 23 - 28, corresponding to the codes of instructions Write., Count, Basic refinement, Count M, Interrogate, Accept. In addition, at output 29, a signal appears when one of the four indications is received. End of Transmission, Read, Read M, Basic Refinement. The output 30 of the decoder 13 generates a signal when receiving instructions, unintended for the proposed device. The output 31 of the decoder 13 generates a signal when it receives any indication other than Received, and the output 32 outputs a signal when it receives one of the three directions. reads Count, Count M, Write.

An exemplary embodiment of the converter 4 codes is shown in FIG. 2. Node 62, made on the CA1 series 564 chip, is designed to generate an oddity check signal for a code arriving in parallel form from the output 58 of the switch

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torus 12, to input 16 of converter 61. And element 63 is designed to start converter 61, and elements 64 and 65 are intended to form control signals that are shifted between themselves in time after the transfer of the 11-bit word. The signal at output 35 of converter 4 is a sign of its operation and is removed from the output of flip-flop 2 of converter 61. Output 36 of converter 4 is designed to transmit a code through two wires 36- (1), 36- (2) to Blo, to 35 (Fig. eleven). The generator in converter 61 is not used, since its function is performed by generator 1 with output 16.

Unit 5 contains amplifiers and a transformer circuit for interfacing with a two-wire half-duplex communication channel. The output 37 of block 5 is designed to transmit a serial code through two wires 37-1, 37-2 to the input of converter 6 (Fig. 10). An exemplary embodiment of converter 6 is given in FIG. 3. The trigger 69, the counter 70 with the decoder 71 form a pulse distributor, the start of which is made by the control signal of the converter 66. This signal is formed after the reception of the converter 66 of the entire 11-bit word. The end of the pulse distributor is automatic. During the operation of the pulse distributor, the decoder 71 produces pulses at the outputs 41- (2) - 41- (3). Register 67 is intended to record parallel

of the first code generated at the output, the output register 67. The code in this register converter 66, at the time of the first pulse at the output 1 of the decoder 71. The node 68, designed to generate an odd code signal, is performed on the CA1 564 series microcircuit,

At the output 38 of the converter 6, a code of the second bit is formed, at the output 39 - a code from the 3rd to 10-fi bits, at the output 40 - a control signal of oddness. The triggers 87 and 83 in the shaper 10 (Fig. 7) are intended to generate pointers in the specified status word, respectively. The indication is rejected, Error on the interface buses. Triggers 91 and 95 are intended to form an Attention Indicator in the status word. This pointer appears 50

55

re, and thus at outputs 38 and 39 of converter 6, is maintained until the last 11th bit of the subsequent word is received.

The operation of the device when receiving instructions - I proceed as follows.

Converter 6 generates an indication code Write at its outputs 38 and 39, and signals appear at outputs 23, 31 and 32 of the decoder 13. When the pulse distributor of converter 6 is working at the moment of the pulse, its output 41- (2) is set to state O of the counter 7 and register 8, and at the moment of the pulse action at the output 41- (3) the trigger is set to 1 the trigger 78 of the register 8 and the start

O

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with pressing any switching element of the keyboard 2. The trigger 92 is intended to form a pointer in the word of the state of the TA. The Fault indicator in the status word is generated by element 93 connected to the outputs of the flip-flops 87 and 88.

Elements 101 and 102 are designed to gate the register code 3 and the code at input 60. Element 104 of block 11 is designed to gate the code of the updated status word from code 49 of generator 10. Element 106 of block 11 is designed to gate the state word code from output 48 of generator 10 Element 107 of block 11 is designed to reset converter 4.

The switch 12 is designed to select information from the outputs 45 and 47 of buffer 9, the outputs 48 and 49 of the imaging unit 10, the output 22 of register 3, and also the input 60. The switch is built on LS2 series 564 chips.

The operation of the device is as follows.

Upon receipt of an 11-bit control or information word from a two-wire communication channel 59, block 5 generates a serial code that enters converter 6. After receiving the last 11th bit, the pulse distributor of converter 6 starts, the first pulse of which records the incoming 11- bit word in the buffer register 67. The code in this register

re, and thus at outputs 38 and 39 of converter 6, is maintained until the last 11th bit of the subsequent word is received.

The operation of the device when receiving instructions - I proceed as follows.

Converter 6 generates an indication code Write at its outputs 38 and 39, and signals appear at outputs 23, 31 and 32 of the decoder 13. When the pulse distributor of converter 6 is working at the moment of the pulse, its output 41- (2) is set to state O of the counter 7 and register 8, and at the moment of the pulse action at the output 41- (3) the trigger is set to 1 the trigger 78 of the register 8 and the start

extension 4. Input of the converter 4 comes from the output 58 of the switch 12 to the status word. with the pointer Continue. This pointer is formed in the shaper 10 directly from the signal at the output 23 of the decoder 13.

After the transfer of the state word to the communication channel, the converter 4 terminates operation, since a signal is given to reset it from the output 57 of block 11. In response to the transmission of the state word with the Continue pointer, the first information word arrives from channel 59, which Output 39 of the converter B is recorded in register 84 of buffer 9. The recording permission signal is generated using elements 80 and 83 of buffer 9. When receiving information words, counter 7 is working, the signals for switching it pass through its elements 72 and 75. Second and third in ormatsionnye analogous words recorded

In a practical manner, the one-byte registers 85 and 86 of buffer 9 are recorded. After the last information word has been recorded, the instruction ends, the signals are generated at outputs 29 and 31 of the decoder 13, about 30 the counter 7 is reset, register 8, set to 1 forwarder trigger 92 92 and triggering converter 4 for transmitting the status word with the pointer WU finished, 35

When receiving the Read M instruction, the signals at the outputs 26, 29, 31 and 32 of the decoder 13 appear and when the converter 4 starts, the input byte contains the information byte of the first register 84 of buffer 9. The permission signal to transmit this byte comes from the output 50 of the element 97 of the block 11, while the output 57 of the block 11 does not signal, and the converter 4 continues to work. After the last 11th bit is transmitted from the output 33 of the converter 4. a signal is sent to counter 7. This signal passes through elements 73 and 75 and acts on the counting input of counter 76, Transmission of the second and third bytes recorded in registers 85 and 86 of buffer 9, happens in a similar way. After the last byte has been transmitted, a signal appears at output 57 of block 11, at which a status byte is transmitted with a pointer to the end of the slave, so

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trigger 92 of driver 10 was set to state 1 even at the moment of receiving the instruction Read M. The reset of the pointer finished with the arrival of the indication of the Pri, which does not trigger the converter 4.

When a Poll instruction is received, only the status word is transmitted.

When any switching element of the keyboard 2 is pressed at output 21, a pulse appears, recording in register 3 a code from output 19 of keyboard 2. This same pulse arrives in shaper 10, set to 1 flip-flop 91, and then flip-flop 95. In response to the instruction Interrogate the transducer 4 transmits a status word with a pointer Attention formed on the code of the element 96 of the former 1Q.

The transfer of the code recorded in register 3 is performed only upon receipt of the instruction Read. In this case, signals appear at the outputs 24, 29, 31 and 32 of the decoder 13. When the converter 4 is first started, the output 58 of the switch 12 receives the code from the register 3. The enable signal comes from the output 53 of the element 101 e) lock 11. At the second start-up of converter 4, a signal appears at the output 54 of the element 102 of the block 11, which permits the passage through the switch 12 of the code set at the input 60 by the operator with the help of additional switching elements. At the third start of the transducer 4, the status word is transmitted with the pointer; The triggers 91 and 95 in the former 10 are reset upon receipt of the indication.

Upon receipt of the indication. The main refinement is the signals at the outputs 25j 29 and 31 of the decoder 13. In response, the transducer 4 transmits the specified state word and the state word sequentially with the pointer VU termin: ilo. Pointers are specified in the specified status word. The indication is rejected and the Error on the interface buses generated by the trigger 87 and 88 and the former 10. If there are any pointers in the specified status word, the pointer is generated.

This is done either by element 93 in the former 10. The updated byte pointers are reset using elements 89, 90 and 94 in the former 10. Element 89 passes a signal when it receives the instructions Read, Read M and Write. A signal passes through element 90 upon receipt of an indication of the Refined State.

Reset pointer Attention is made when receiving the instructions Princi, but provided that before him came the instruction to Count.

Claims (1)

Invention Formula The ycTpoffcTBO for inputting information contains a pulse generator, a keyboard, a first register, a first pulse generator output connected to a keyboard input, whose information outputs and synchronization output are connected to information inputs and a synchronous input, respectively, of the first register, in order to expand the field of application communication channel organization account, the first and second code converters, the first counter, the first decoder, the second register, the interface block, the data buffer, the forms are entered into it. a state word generator, a control unit and a switch, the second and third outputs of the pulse generator are connected to the first inputs of the first and second code converters, respectively, the first output of the first decoder is connected to the third input of the second register and the seventh input of the status word generator, the second output of the first decoder connected to the second inputs of the second register and the control unit; the third output of the first decoder is connected to the eighth input of the status word generator and the third input of the control unit; The third output of the first decoder is connected to the fourth input of the control unit, the fifth to the eighth outputs of the first decoder are connected to the inputs from the ninth to the twelfth form conditioner, the ninth output of the first decoder is connected to the fourth inputs of the second controller. the gistra and the first code converter and with the third input of the first counter, the tenth output of the first decoder is connected to the fourth input 5 of the first counter and the thirteenth input of the data buffer, the first and second outputs of the first code converter are connected to the first and second inputs of the condition word generator right, the third exit is connected to the input of the interface unit, and the fourth with the sixth input of the first counter, the output of which is connected to the fourth input of the data buffer, the sixth input the status word generator and the first input of the control unit, the input / output of the interface unit is the device output, and the output is connected to the second input of the second code converter, the first and second outputs of the second code converter are connected to the first and second inputs of the data buffer, respectively and the first decoder, the third output of the second code converter is connected to the fourth input of the status word generator, and the fourth to the third input of the data buffer, the fifth input of the status word generator. the first entry is the second register and wto The first input of the first counter, the first output of which is connected to the fifth inputs, the data buffer and the first counter, and the second output connected to the fourteenth input of the status word generator, the data buffer outputs are connected from the first to the third input of the switch, the status word generator outputs connected to four the fifth and fifth inputs of the switch, the first to the seventh outputs of the control unit are connected from the eighth to the fourteenth inputs of the switch, respectively, the eighth output of the control unit is connected to the second input of the first converter, the output of the first register is connected to the seventh input of the switch, the sixth input is the device input , and the output is connected to the fifth input of the first code converter, t; In this case, the input of the status word generator is combined with the first input of the first register, the first output of the second converter is connected to the first input of the first counter. J7 FIG. 2 Ш9) Tpsql wmm Fi.j.5 8 5 In fS at 7 6 Fi & .8 t J J J J JTLJ JlJlJ JTJ lJ J-L -G2; 59 Na na A connection -Og-Pg-l-iG-Ogt node Code 2 SHO under O No 1 Code About tt-1I1f-1 Fig.Yu 6 (i) Jn A „..- Or-iJ-ar-b-Tj -ar Contact Code Code About KodJ Hodi CBDO HodJ se Fi & .11