SU1522220A1 - Device for interfacing information source with receiver - Google Patents

Abstract

The invention relates to computing and can be used as a device for converting and buffering data in control systems, as well as for interfacing computers with communication channels. The purpose of the invention is to expand the functionality by ensuring that the time of receipt of information is fixed. Achievement of the goal is achieved by introducing a device containing a counter, a trigger, a decoder, two buffer storage nodes / BZU / and five switches, a register, a write address coder, a delay node, and four switches. The device trigger, by communicating with the output of the decoder, sets one LPD in write mode, and the other in read mode. A counter with the same signals from the decoder is zeroed out and starts counting from the beginning after the end of each recording cycle in one of two RAMs. This allows us to consider the code at the outputs of the counter, which is recorded in the BZU at the end of each information parcel at a certain address, as the time code of the incoming information. The delay node associated with the information input of the device generates recording signals into the corresponding RAM and control signals of the respective switches, which in turn provide a sequence for recording input information and information from the counter output. At the same time, information is read from the second RAM. 1 hp ff, 3 ill.

Description

The invention relates to computing and can be used as a device for converting and buffering data in control systems, as well as for interfacing computers with communication channels.

The purpose of the invention is to expand the functionality of the device by ensuring that the arrival time of information is fixed.

FIG. 1 shows a block diagram of the device; in fig. 2- functional on the delay node circuit; in fig. 3 - diagrams explaining the operation of the delay unit.

The device contains (Fig. 1) buffer storage nodes (BZU) 1 and 2, first, fifth, second, second, fourth, third, sixth, seventh, ninth and eighth switches 3-11, register 12, encoder 13 write addresses , node 14 delay, the decoder 15, the trigger 16, the counter 17 and the generator 18 pulses.

The node 14 of the delay contains (Fig. 2) two delay lines 19, 20, the element OR 21 and the expander pulses 22.

The device works as follows.

The initial state of the circuit is determined by the state of the trigger 16: when the state of the outputs of the trigger 16 is corresponding to 01, the RAM 1 is in the write mode, the RAM 2 is in the read mode. When the state of the outputs of the trigger 16 changes by 10, the modes of operation of the BZU1 and BZU2 change.

At the same time, in the recording mode in BZU1, its first output is connected to the information input of the switch 5; the information input of the switch 3 is connected to its input-output; its first information input is connected to the output of the switch 9; the first information input of the switch 7 is disconnected from its output. The trigger 16 is controlled by the decoder 15, which generates the control signals (FIG. S) in accordance with the code at the address output of the address bits of the register 12. These same control signals are zero signals for the counter 17.

In the write mode in the BDU (Fig. 3), the address-information word arriving in the register 12 starts node 14. A write pulse (Fig. 36) is formed at the second output of the latter, which through the open switch 5 enters the control input of the first RCD1. With the code received from the address output of the address bits of register 12, a signal is generated at the output of the decoder 15, according to which the trigger 16 is set to state 10, and the counter 18 is zeroed and starts a new countdown (Fig.). The codes at the outputs of the encoder 13 form two addresses: one to record the input information in the RAM 1, the second address is formed, if necessary, to record the arrival time code for this information. If any address-information words do not need to be marked with a time code, the encoder 13 forms for them at its second output addresses or nonexistent libr one fixed address common to these words. Similarly, if there is no need to record any address-informational words, either non-existing write addresses are formed at the second output of the encoder 13.

0

five

0

five

or one common address for these words to fix.

The address for recording information goes through the open switches 8 and 9 to the address input of the RAM BD. In this case, at the control inputs of switches 8 and 10 there is a low level signal (Fig. Sv). Then, at the first output of the node 14, a control signal is formed (fig. Sv), through which the outputs of the switches 8 and 10 connect their second information inputs. The input-output of the first BZU in the presence of an address at the second output of the encoder 13 receives information from the output of the counter 17. By the second recording pulse from the second exit of the node 14, the information from the counter 17 is recorded in the BZU 1 (Fig. 3g, Fig. 3g).

At the end of the control pulse from the first output of the node 14, the switches 8 and 10 return to their initial state. At the next address-information word of each cycle, if there is an address at the second output of the encoder 13, the code from the information arrival time counter 17 is entered into the first RAM 1.

Simultaneously with the recording of information in the BZU 1, information is read from the BZU 2 (Fig. 3). In the readout mode from the OVC 2 from the second RDB 2, the information input of the switch 6 is connected to the second output, the input-output of the switch 4, the second information input of the switch 7 and the second information input of the switch 11 are connected to their outputs. Through switch 6, a read signal is received from the read input to the control input of the second rectifier 2.

The first read address through the com- mutator 11 arrives at the address input of the EZD 2. According to the received address, information appears at the output of the read signal, which through the switch 4 and the switch 7 arrives at the output of the device.

Switching control BZU 1, 2 is carried out upon receipt of the address-information word with a fixed address, leading to

the decoder 15 is triggered and the trigger 16 is switched. The state of the trigger 16 outputs is changed to 01. In this case, the RAM 1 is switched to the read mode, and the RAM 2 - to the write mode (Fig. 3e, g); its second information input is connected to the output of the switch 9; the input - output of the switch 3 is connected to its information output; the first information input is connected to the output of the switch 7; the information input of the switch 6 is connected to its first output. The information input of the switch 5 is connected to its second output; the first input of the switch I1 is connected to its output; the information input of the switch 4 is connected to its input / output. Writing and reading information occurs as described above.

Claims (2)

1. A device for interfacing the source and receiver of information containing a counter, a decoder, a trigger, five switches and two buffer storage nodes, with the output of the decoder-jg formation inputs of the first and five torus being connected to the trigger input of the forward switches. the forward and the forward output of which is connected to the control input of the first switch, the control input of the second switch and the first control input of the third switch, the inverse output of the trigger is connected to the control inputs of the fourth and fifth switch and the second control input of the third switch, the first the information input of the formation number and connected to the second one is connected to the output of the first one. the seventh con terminal; input of the switch connected by the input-output to the input-code of the first buffer node; the control input of which is connected to the first outputs of the second to fourth switch, the second outputs of which are connected to the control input of the second buffer storage node; the input-output of the connected to the input-output of the p of the switch, the output of which is connected to the B1 of the second U1-formation input of the third switch, the output of which is the output 4S the outputs of the trigger of the connection, respectively, with the control inputs of the seventh and eighth switches, the output of which is connected to the address input of the second buffer storage memory, the second information input is the input of the device for connected and to the output address of the receiver's output, the output output of which is connected to the address input the first buffer storage node, the counting input of the counter is connected to the output of the pulse generator, the zeroing input is from the encoder, and the output to the information input to the quater. the release of the second decade maiden 50 2. A device according to Claim 1, so that it is such that the delay node contains two delay lines, an IC element and a pulse expander, the inputs of the delay line 1–1 delay being the input of the WEP and connected to the first input the OR element, the second. input of which is connected to the output of the first delay line, the second output of the second delay line contains devices for connecting to the information input of the receiver information, the information input of the fourth switch is the input of the device for connecting to the read output of the first receiver — information differing So that, in order to expand the functionality by ensuring that the information arrival time is fixed, four switches are inserted, a pulse generator, a write address encoder, a delay node and a register, a register information input combined with the input of the delay node and the input of the device to connect to the information output of the information source, the output of the register address bits is connected to the input of the decoder and the input of the write address encoder, the first and second outputs of which are connected according to ny first and Etor m data inputs of the sixth switch, whose output is connected to the first data inputs of the seventh to eighth. The control switch is connected to the control input of the ninth switch and the first output of the delay node, the second output of which is connected to the information input of the second switch, and the code of the register bits is connected to the first information input of the ninth tator, the output of which is connected to information inputs first and fifth switches. The forward and the late formations are connected to the second information input of the seventh con; the utator, 35 jg by the formation inputs of the first and fifth switches. the forward and the late formations are connected to the second information input of the seventh con; the utator, the outputs of the trigger of the connection, respectively, with the control inputs of the seventh and eighth switches, the output of which is connected to the address input of the second buffer storage memory, the second information input is the input of the device for connected and the output address of the receiver's readings with the educational inputs of the first and n of the switches. the forward and the late formations are connected to the second information input of the seventh con; the utator, S the output of which is connected to the address input of the first buffer storage node, the counting input of the counter is connected to the output of the pulse generator, the zeroing input is connected to the encoder, and the output to the information input to the router. the output of the second and the ninth by the composite inputs of the first and fifth switches. The forward and the late formations are connected to the second information input of the seventh con; the utator, 2. The device according to claim 1, 1, of which it is such that the delay node contains two delay lines, an IC element and a pulse expander, the inputs of the delay line 1–1 delay being the input of the WEP and connected to the first the input of the OR element, the second. input of which is connected to the output of the first delay line, the second output of the second delay line contains It is united with the input of the pulse expander OR, respectively, the first ow, the output of which and the output of the element and second outputs of the node. (rig 2 iTJt-H fig Of n A S n П П П П П П П П П П П П П at id LP P kn P P By. Fi.Z