SU1444790A1 - Device for interfacing a group of operational units with common storage - Google Patents

Abstract

The invention relates to the field of computing, in particular, to devices for interfacing specialized operational units that are part of a complex computing device that operates with a unicast command format. The aim of the invention is to increase reliability due to the operative redistribution of data exchange between the operational blocks. The device contains a register of commands, the decoder. commands, a group of nodes for fetching an operation block, a memory of states, a switch for receiving a result, two AND elements, a switch for the result address, a selector switch, a priority block. 1 hp files, 7 Sh1.

Description

H

WITH

The invention relates to the field of computing, in particular, to devices for interfacing specialized operational units that are part of a complex computing device that operates with a unicast command format.

The aim of the invention is to increase reliability due to the operative redistribution of data exchange between operational units.

FIG. 1 shows a block diagram of an apparatus for interconnecting groups of operating units with shared memory; in fig. 2 is a diagram of the operation block sampling assembly of FIG. 3 is a schematic of the access selector; in fig. 4 is a diagram of the result receiving switch; in fig. 5 is a diagram of the switching node of the second operand; Fig 6 is a diagram of a command decoder; in fig. 7 is a priority block diagram.

The device contains (Fig. 1) a registrar of 1 commands, a descrambler of 2 commands, a group of nodes 3, a sample of the operational block, a memory of 4 states, a result receiving switch 5, elements AND 6.7, a result address switch 8, a call selector 9 , block 10 priority, inputs and outputs 11-35. devices.

Node 3 sample operating unit contains (Fig. 2) the element OR 36, the group of elements And 37.

The selector 9 reversed contains (FIG. 3) a group of comparison elements 38.

The result receiving switch 5 contains (FIG. 4) a group of comparison elements 39, a group of switching nodes 40 of the second operand. The diagram (Fig. 4) also indicates the outputs 41 of the elements 39 of the group comparison.

The node 40 of the switching of the second operand contains (Fig. 5) two groups of elements And 42,43, the element 44 of the delay group triggers 45, the switch 46.

The decoder 2 commands contains (Fig. 6) a group of elements And 47, an element OR 48, a group of elements And 49, a decoder 50 signs of entry, element And 51,52, a buffer register 5

The priority block 10 contains (FIG. 7) the element OR 54, the group of elements AND 55, the group of flip-flops 56., the element ILIG-NOT 57, the switch 58 of the number.

0

The device works as follows.

From the common memory, via bus 16 to register 1 of commands, the next command is received with the frequency of the external synchronization signal 18, containing three fields: PZ - sign of entering, CPC - opcode, A - address of the first one-.

0 rand, then the command is sent to the decoder 2 commands for further processing. In command decoder 2, a command reception resolution 25 is generated based on a preliminary analysis of the state of the operating units in the computing device. A preliminary analysis of the readiness of the computing device to receive the current command is performed in the decoder of 2 commands by viewing the contents of the FL field of the register of 1 commands on the decoder 50 of the flag of entry and in the group of elements And 49. Elements And 49 generate signals

5 permissions to receive a command to the group of operational blocks requested by the current command if there is a ready signal from this group of operational blocks from the bus 28. Signals

The 0 resolutions from the outputs of the AND 49 elements are collected on the OR 48 element, which produces the common resolution signal 25, and the signals from the outputs of the AND 49 elements on the bus 27 arrive at the corresponding control inputs of the nodes 3, the samples of the operation unit, these nodes select the required group operating units. Nodes 3, the number of which corresponds to the number of groups of operating units, ensure that the operating units are selected from the group in the presence of a group of ready signals from the corresponding operating units, which are transmitted via bus 12, and in the same units 3 a ready signal is formed of a group of operating units, if it has at least one free operational block, these signals from each node 3 are associated with

0 by the corresponding inputs of the decoder 2 commands bus 28 readiness operative units.

0

five

The signal that triggers the operation of the selected current operating unit. As it arrives at its control input via bus 23, the signals from this bus simultaneously go to the memory inputs of 4 states, which indicate in the next command cycle where the result of the current command should be sent. This is ensured by the fact that in the current command cycle information about which operating unit is selected in it is transmitted to the register inputs (4 state memory) via bus 23, on which this information is present during the current command cycle and for some time at the beginning the next command cycle (due to delays in the decoder of 2 commands), while the register, which is the 4-state memory, is built on D-triggers, which are triggered by the leading edge of the recording signal from the bus 32 of the command reception gate and remember the state of the bus 23 which risutstvovalo on it at the beginning of the next cycle.

After being executed by the current operational unit specified in the CPC field, its result is transmitted to

five

0

the busses from the bus 13 of the result address (the operational block from the previous command — this address was recorded into it via the bus 22), arriving at the inputs of the comparison elements 39 (their number corresponds to the number of groups of the operating blocks) of the switch 5, and the signals from the information bus 14 the operand (from the operating unit, which is involved in the current command — produced by the operating unit's control unit after initiating its operation) coincided, therefore, that part of the switch 5 that organizes the connection is selected operation blocks in the current group, and if the inputs of one of the switching nodes 40 of the second operand (the number of which connected to the output of one comparison element 39 corresponds to the total number of operational blocks) received a signal from memory output 4

the result register and one- 25 state from the bus 33 lying on it.

the radio unit generates a readiness signal, which is transmitted to bus 12. Next, using the switch 8 of the result address and switch 5, the operational unit is connected, occupied in the previous command, with the operational unit initiated in the new current command, and this connection exists before until the result from one operation unit is transmitted to another, after which the connection is interrupted.

In more detail, this operation is carried out as follows: switch 8 passes the PZ field code of the current command through bus 29 to the operating unit that was selected in the previous command, which is provided by controlling the output signals from bus 33 from state memory 44, if any the signal about the permission to receive a new command from the bus 25. Thus, in the operational unit occupied in the previous command, the information about the address of the result of its calculation via the bus 22 information output of the switch of the address is recorded tata.

The transfer of the result code of the operation of the previous command is switched by switch 5, with one of the pair of switched operating units being the receiver and the other with the transmitter of the number code. Switching is performed if sig30

35

40

the start of switching is carried out by the signal from the bus 32. The strobe of receiving the command by the first elements AND 42 and la 40 of the switching of the second operand. The switching state of the two operational blocks is maintained by a group of triggers 45, which are set to single or zero state by signals from the output of the AND elements of the switching node 40 of the second operand 42 and 43, respectively, switching is performed by a signal from bus 12, which goes to the input of elements 43 through the delay element 44 in the absence of a signal from the control input 41 of the reception permission of the second operand. The result code of the operation of the previous com- munity is transmitted through one of the channel of the switch 46 in the presence of

5 nor from any trigger 45 post current as this result is ready in the previous operational block. In the period of the connection of two operating units, another operating unit or

50 manda cannot address them, as they produce a signal that is busy on the bus 12.

If the result of the previous operation must be transferred to a common memory,

55 this transfer is realized through the priority block 10, in which it implements a conflict-free access to the common memory from the set of operational blocks of the computing device.

0

five

0

the start of switching is effected by a signal from the bus 32. The strobe of receiving the command by the first elements AND 42 of the switching node 40 of the second operand. The switching state of the two operational blocks is maintained by a group of triggers 45, which are set to one or zero state by signals from the outputs of elements And of switching node 40 of the second operand 42 and 43, respectively; the switching is reset by a signal from bus 12, which goes to the input of elements AND 43 through a delay element 44 in the absence of a signal from control input 41 of receiving the second operand. Code . the result of the operation of the previous command is transmitted through one of the channels of the switch 46 if there is a resolution5 from any trigger 45 after the current, as this result is ready in the previous operational block. During the period when the two operational blocks are connected, no other operational block or command can access them, since they produce a bus 12 signal.

If the result of the previous operation needs to be transferred to a shared memory,

5, the transmission is realized through the priority block 10 in which it is implemented. conflict-free access to shared memory from a set of operating units of a computing device.

This operation is carried out as follows: the input of the block 10 receives signals for accessing the common memory via the bus 35 from each operating unit, which are set to the appropriate position of the trigger 56 by means of the elements 55, while at least one of the flip-flops 56 is set to state 1, then others can no longer be set to this state, since flip-flops of triggers are prohibited by the signal from the output of the OR-NOT 57 element. Signal 1 at the output of one of the flip-flops 56 is also the resolution for sending the result code from Compliant operation unit in a common memory.

The common memory access signals from the operating units are generated in the access selector 9 using comparison elements 38, the first inputs of which receive signals from the bus 13, on which there is information about where the result of the previous operation should be directed and the second inputs connected to Earth bus and, if on some comparison element 38 the code 0..0 is met (received via bus 13- and corresponding to the common memory access command), then this comparison element 38 generates a data memory access signal from the corresponding boiling operating units which is transmitted over the bus 35 to the appropriate input of unit 10, it requires a signal on the control input 34, the selector 9 handling.

Claims (2)

Invention Formula 1, A device for interfacing a group of operating units with a common memory containing a command register, a command decoder, a state memory, the group of information inputs of the command register forming a group of device inputs for connecting to a group of information outputs, a common memory, the first group of outputs the command decoder forms a group of device outputs for connecting to the group of address inputs of the shared memory, while the first, second and third groups of information outputs of the command register are connected respectively to the first, second th and third groups five 0 five 0 five 0 five 0 five information inputs of the command decoder, characterized in that, in order to increase reliability due to the operative redistribution of data exchange between the operating units, a group of nodes of the operating unit selection, a result address switch, a result receive switch, a selector switch, a priority block, two AND elements are introduced into it The group of information outputs of the priority block forms the group of outputs of the device for connection to the group of information inputs of the common memory, the installation input of the priority block in The input of the device for connecting to the readiness output of the common memory, the output of the priority block is connected to the gate input of the command decoder, and is the output of the device for connecting to the common memory access input, the group of information outputs of the result address switchboard forms the group of outputs of the device for connecting to the first the information inputs of the operating units of the group, the group of information outputs of the result receiving switch forms a group of outputs of the device for connecting to the second information group operational information blocks, the first group of information inputs of the result receive switch is connected to the first group of information inputs of the priority block and forms a group of device inputs for connecting the first operational outputs of the group blocks, the second group of information inputs of the result receive switch forms a group of device inputs for connecting to the second information inputs of the operating units of the group, the third group of information inputs of the receive switch result connected to the group of information inputs of the access selector and forms a group of device inputs for connecting to the third information outputs of the operating units of the group; groups of information outputs of the sampling nodes of the operation unit of the group are connected to the group of information inputs of the state memory and form a group of outputs of the device for connecting to the inputs samples of one-, rational group blocks, information inputs of sampling nodes of the operational block of a group are connected to a group 7 the inputs of the result receive switch and form a group of device inputs for connecting the ready operational blocks of the group to the output, the second group of command decoder outputs form the device's output group for connecting the operation blocks of the operational blocks of the group to the inputs of the operation register register input connected to the first inputs of the first, second elements And is a sikhrovhodom device, with a third group of command decoder connected to the enabling inputs of the corresponding sampling nodes operating a group of blocks whose information outputs are connected to the fourth group of information inputs of the command decoder, a third group of information inputs of which are connected to the first group of information inputs of the result address switch, the second group of information inputs of which are connected to the fourth group of information inputs of the result receiving switch and to a group of information signals a state memory whose recording input is connected to the control input of the result receiving switch and to the output / i q q 4790 The second element And, the second input of which is connected to the control input of the switch of the result address and the first output of the command decoder, the second output of which is connected to the second input of the first element And, the output of which is connected to the enabling input of the access selector, the output group of which is connected to the second group of information priority block inputs. 2. The device according to claim 1, wherein the sampling node of the operation unit contains an RSHI element and a group of K elements AND, the first inputs of the elements AND group being the enabling input of the node the outputs of the elements AND groups form a group of information outputs of the node, the second inputs of the elements AND of the group are connected to the corresponding input of the group of inputs of the element OR, and are the information input of the node, the output of the NL element is the information output of the node, while in the sampling node of the operating unit the output of the i-ro element AND of the group (, K-1) is connected to the third input of the (i + 1) -th element I. groups. FIG. 2 "J (rig.U 20 VNIIPI jaKaa 6507/49. Circulation 704 Subscription Random polygons pr-tie, Uzhgorod, st. Project, 4 FIG. 6