SU1425696A1 - Device for interfacing input/output channels with users - Google Patents

Abstract

The invention relates to computing and can be used in the construction of two-machine computing systems. The aim of the invention is to increase the capacity of the device. The goal is achieved in that a device containing two communication units with a channel, a first communication unit with subscribers, a switching unit, a first sampling control unit, a mode setting unit, six groups of AND elements, two AND elements, two OR elements, two triggers , two address decoders, two command decoders, a second communication unit with subscribers, a second sampling control unit, a priority unit, a time stamp generator, two AND elements, two counters, two OR elements. The invention provides a flexible organization of information exchange between two computers and a field of external subscribers, conditionally distributed between computers. A device for interfacing when initiating the exchange from the computer side ensures the selection and connection of a free subscriber in one computer reference. When the subscriber initiates the exchange, the subscriber's request signal for the exchange comes first to the conditionally fixed computer, and if it is busy or faulty, it is transmitted to the second computer. 1 z.p, f-ly, 7 ill. § (L

Description

1U

The invention relates to computing and is intended to organize the exchange of information between two input / output channels and a common field of subscribers.

The aim of the invention is to increase the capacity of the device by allowing the channel of the computer to select a free subscriber, several subscribers at the same time and to provide access to the subscriber's demand for an exchange to the free and healthy computer.

Fig. 1 is a block diagram of an interface device; Fig. 2 is a functional block diagram of the sampling control unit; FIG. 3 is a functional circuit of a switching unit; Fig. 4 is a functional diagram of a communication unit with a subscriber; FIG. 3 is a functional priority block diagram; FIG. 6 is a functional block diagram of the mode setting; Fig. 7 is a functional diagram of a communication unit with a channel.

The device (figure 1) contains blocks

1.1 and 1.2 communication with channels, mode setting unit 2, communication units with subscribers 3.1 and 3.2, sampling control units 4.1 and 4.2, switching unit 5, priority block 6, decoders 7.1 and

7.2addresses, decoders 8.1 and 8 „2 commands, first and second commands, fourth and fifth groups of elements And 9.1 and 9.2, 10.1 and 10.2, triggers 11.1 and 11.2, elements And 12.1 and 12.2, elements

OR 13.1 and 13.2, 14.1 and 14.2, elements And 15.1 and 15.2, counters 16.1 and 16.2, the third and sixth groups of elements And 17.1 and 17.2, generator 18 time stamps, bus 19 information from the first channel, outputs 20-23 of control signals from the first channel, the outputs 24-27 of the control signals from the second channel, the bus 28 information. from the second channel, the information bus 29 to the first channel, the information bus 30 to the Second channel, the output 31 of the information signal for the first channel, the output 32 of the information tracking signal to the second channel, the output 33 and 34 of the reset signal, the information bus 35 to the first subscriber, outputs 36 and 37 control signals to the first subscriber, bus 38 of information to the second subscriber, outputs 39 and 40 of the control signals to the second subscriber, bus 41 of information from the first subscriber, outputs 42 and 43 of control signals

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signals from the first subscriber, the output 44 of the exchange request signal from the first subscriber, the second subscriber information bus 45, the outputs 46 and 47 of the control signals from the second subscriber, the output 48 of the exchange demand signal from the second subscriber, the outputs 49.1 and 49.2 of the first sampling control signal, outputs 50.1 and 50.2 of the first sampling signal, outputs 51.1 and 51.2 of the busy signal, outputs 52.1 and 52..2 of the second sampling signal, outputs 53.1 and 53.2 of the control signal, outputs 54.1 and 54.2 of the second control signal sampling, outputs 55.1 and 55.2, 56.1 and 56.2 and

57.1 and 57.2, 58.1 and 58.2, 59.1 and

59.2 control signals, outputs 60 and 61 of priority signals, outputs

62 and 63 priority sampling signals, control signal output -64, subscriber demand signal outputs 65.1 and 65.2, channel sampling signal outputs 66.1 and 66.2, output control signals outputs 67.1 and 67.2, 68.1 and 68.2, inputs 69.1 and 69.2, 70.1. and 70.2 commands, data bus 71.1 and 71.2, counter overflow signal outputs 72.1 and 72.2.

Blocks 4.1 and 4.2 of the control sample (figure 2) contain the element OR 73, trigger 74, element AND 75, trigger 76, elements AND 77-80, trigger 81, element AND 82, element OR 83, 5 trigger 84, element OR 85, triggers 86 and 87, element AND 88, elements OR 89 and 90, element AND 91, elements OR 92-94, elements AND 95-100.

The switching unit 5 (FIG. 3) contains elements AND 101-108, elements OR 109 and 110, elements AND 111 and 112, elements OR 113-116, elements AND 117 and 118, elements OR 119-121, elements AND 122-131 , element IGSh 132, elements And 133 and 134, elements ШШ 135 and 136.,

Blocks 3.1 and 3.2 of communication with the subscriber (FIG. 4) contain an OR element 137, a clock generator 138, AND elements 139-142, register 143, AND 144 element group, triggers 145-150, And 151 element group.

Block 6 priority (figure 5) contains the element And 152, the element is NOT 153, 5 element And 154, the element SH 155, the trigger 156, the element And 157, the element NOT 158, the element And 159, the element OR 160, the trigger 161, the element And 162

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The mode setting unit 2 (FIG. 6) contains the element HE 163 and the priority switch P.

Blocks 1.1 and 1.2 with the channel (Fig.7 contain amplifiers, receivers 164 and amplifiers, transmitters 165.

Blocks 1.1 and 1.2 with channels are intended to receive and transmit control, address and information signals between the interface device and two channels. Block 2 is used to set the priority for the first or second channel depending on the position of the switch P. Blocks 3.1 and 3.2 communications with subscribers are intended for receiving, generating and transmitting control signals and information (data) between the interface device itself and the subscribers. Sample control blocks 4.1 and 4.2 are used to select one of the channels or two channels simultaneously. a free subscriber or two subscribers at the same time, as well as for signal transmission Requirement of exchange to a free channel.

Switching unit 5 is intended for switching information flows and control signals between channels and subscribers, depending on the sampling signals coming from the sampling control units. Using these signals, the selection of the switching direction and the selection of a subscriber for a particular channel is carried out.

The priority block 6 serves to generate priority signals from the signals from the first and second address decoders, depending on the priority set by block 2.

Deflectors 7.1 and 7; 2 addresses are designed to generate control signals. Addresses depending on the code from the channel. The decoders 8.1 and 8.2 of the commands serve to carry out and transfer commands to the communication units with subscribers, depending on the code from the canal.

Groups of elements And 9.1 and 9.2, 10.1 and 10.2 are intended to transfer information from the channel to the address and command decoders depending on the control signals.

Triggers 11.1 and 11.2 are used to form, store and transfer signals to the channel Subscriber Requirement (TRB-A).

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Elements And 1 2.-1 and 12.2 are designed to transmit signals Sample from the channel (FBG-K), depending on the state of the trigger 11.1 and 11.2. The elements OR 13.1 and 13.2 form the trigger setup signals.

11.1 and 11.2 in one state. The elements OR 14.1 and 14.2 form

Q trigger setup signals 11.1 and

11.2 zero state. Elements 15.1 and 15.2 are used to transmit signals from the generator 18 time stamps to counters 16.1 and 16.2, depending on the state of the trigger 11.1.

and 11.2.

Counters 16.1 and 16.2 are intended for counting a predetermined (bitwise) time interval.

Groups of elements And 17.1 and 17.2 are used to transmit information (data) from the channel to block 5, depending on the control signals.

The generator 18 is designed to generate signals with a predetermined time interval - time stamps.

Bus 19 is a block output

1.1 and serves to transmit from the first channel the code of addresses, commands and

Q data.

Output 20 is intended for transmission from the first channel of the control signal Address from the channel (ADR-K), output 21 for transmitting from the first channel of the control signal Control from the channel (UPR-K), output 22 for transmission from the first channel of the control signal Signal Information from the channel (INF-K), output 23 - for transmission from the first channel of the control signal Sample from the channel (FBG-K). Output 24 is intended for transmitting a FBG-K control signal from the second channel, output 25 for transmitting a control signal INF-K from the second channel, output 26 for transmitting a control signal UPR-K from a second channel, output 27 for transmitting from the second channel of the control signal 0 ADR-K.

Bus 28 is a block output

1.2 and is designed to transmit and the second channel code addresses, commands and data. Bus lines 29 and 30 have output from unit 5 and serve to transfer information from switching unit 5 to the first and second channels, respectively. Exit 31 is intended for

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signal reduction Information from the subscriber (INF-A) from the switching unit 5 to the first channel. Output 32 is used to transmit the INF-A signal from switching unit 5 to the second channel. Outputs 33 and 34 are designed to transmit signals to blocks 4.1 and 4.2 of the control of the selection of the reset signals.

Tires 35 and 38, 41 and 45 are outputs of blocks 5 and 3, respectively, and are used to transfer information (data) between unit 3, switch-3, and blocks 3.1 and 3.2, czm with subscribers.

Exit 36, 37, 39, 40 and 42, 43,

46., 47 are for transmitting control signals from the block 3

and blocks 3.1 and 3.2 of communication with subscribers. Output 44 is used to transmit a signal to require an exchange (TO) from the first subscriber. Output 48 is for transmitting a TO signal from a second subscriber. Exit 49 „1, 49„ 2, 50,1 ,, 50 L, 51. L 51.2,52.15 52, 2, 53 .1, 53.2,54.1,54.2.55 about 1.55.2.56 with 1.56.2 „

57.1,57,2, 58.1, 58 L, 59.1, 59 .. 2 are used to transmit control signals from 6HokoB 4.1 and 4o2 sampling control,

The highs 60 and 61 are for transmitting priority signals from block 2, Outputs 62-64 are used to transmit priority sampling signals and a control signal from priority block 6. The outputs 65.1, 65.2 are designed to transmit a signal to the channel. TRB - A, Output 66.1, 66.2 are used to transmit the FBR-K signal from the outputs of the And 12.1, 12, 2 elements, Outputs 67 "1,

67.2,68.1, 68.2 blocks 7 are designed to transmit address control signals from decoder codes.

7.1,7,2 addresses. The OR element 73 of blocks 4.1, 4.2 is intended to form the Zan signal and transmit it to outputs 51.1 and 51.2 of blocks 4 and 1 and 4.2, respectively. Triggers

74 and 76 are used for forming and storing s and Equalizing signals of a block for block 5, Elementas And, 75, 77-80 82 are intended for generating control signals of blocks 4.15

4.2. Element OR 83 is used to receive the priority signal of the sample and the control signal of the address from the inputs of blocks 4.1 and 4.2, Triggers 34 and

86 are intended for the production and storage of intermediate control units.

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the signaling of blocks 4.1, 4.2, trigger 87 serves to store the signal TO from the subscriber. The elements And 88, 91 95-100 are intended to form the internal control signals of the blocks 4.1;,. 4.2. The elements OR 89, 90, 92-94 serve to generate setup signals for triggers 845 86 and 87,

The device works as follows.

The initial exchange of information between channels and subscribers through the device can be carried out both by the channel and by the subscriber, hence two modes of operation of the device are possible.

Consider first the case when the initiator of the exchange is a channel. Here two options are possible. In the first variant, the channel sends the first modification of the address to the device (CS), and the channel wants to establish a connection (write or read information) with one of the subscribers with a free subscriber. In the second variant, the channel sends the second modification of the address to the US to establish communication simultaneously with two subscribers, as a rule, such communication is necessary for simultaneous recording of information on all subscribers or at least on all subscribers free at a given time.

In the first variant, the first modification of the address code is de-encrypted on the de-impraser 7.1, and the signal from its output 67 And goes to block 4.1, to the input of the element WIT 83 Scheme, blocks 4.1 and 4.2 and the connection between them and other blocks are constructed in such a way that the first channel always first tries to establish communication with the first subscriber, the second channel of the first channel tries to establish a second channel, and if the corresponding subscribers are busy, proceed to the analysis of the next subscriber. The signal from the output of the SHS 83 element goes simultaneously to the inputs of the AND 77-79 and 97 elements. If by that time the signals from the first and second subscribers had already arrived, the triggers 87 of blocks 4.1 and 4.2 are set to one and exchange initiated. the channel cannot be. In this case, the AND 77 element is open, and at its output a signal is generated, which enters through the OR element 73 to the output 51.1, 51.2 of the corresponding block 4.1, 4.2 and further through the corresponding amplifiers of blocks 1.1, 1.2 into the channel. The signal Zahn is formed also in the event that trigger block 86

4.1 is in the single state (this means that the second channel is communicating with the first subscriber), and the trigger 84 of the block 4.2 is in the single state (this means that the second channel is communicating with the second subscriber), then the element 78 it turns out to be open and the signal Zahn from its output goes to another input of the element OR 73 and further to the channel. If the flip-flops 86 and 87 of block 4i1 are in the zero state, then the AND 79 element is open, and the signal from the output of the OR 83 element passes to the input of the OR 93 element, from the output of which this signal sets the trigger 84 to one state and output 54.1 of block 4.1 goes to block 6 to set the trigger 161 to the zero state (in this mode of operation, it is not necessary to set the trigger 161 to the zero state) and input element I 13.1, from whose output this signal sets the trigger state to 11.1 . The TRB-A signal from the output of the trigger 11.1 is transmitted to the channel. With the TRB-A signal, the channel is informed that the subscriber is free and the CM is ready to receive and execute the command. If trigger 86 is in the single state, AND 79 is closed, AND 97 is open, and the signal from the OR 83 output of the element passes through AND 97 to output 58.1 of block 4.1. From the output, this signal arrives at the input of the element And 96 of the block 4.2, thus an attempt is made to select the second subscriber when the first subscriber is busy. Element AND 96 will be open if the second element is not occupied by the second channel, i.e., if the trigger 84 of the block 4.2 is in the zero state. Then the signal from the output of the element AND 96 through the element OR 89 sets the trigger 86 to one state, at the same time this signal through the output 49.2 of the block

4.2 arrives at the second input of the element OR 13.1, sets the trigger

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11.1 in a single state, the TRB-A signal from the output of which through the block

1.1 is transmitted to the channel. Thus, a connection is made to the channel of the free subscriber. Next, the channel sends to the CM a command (Write or Read) and a VBR-K signal, which through the appropriate amplifier arrives at the output of block 23 and then at the open single output of trigger 11.1. And 12.1. From output 66.1, the VBR-K signal sets the trigger 11.1 and the counter 1b, 1 through the OR element 14.1 to the initial state. When the trigger 11.1 is in the single state, the AND 15.1 element is open, and the time stamps from the generator 18 fill the QQ 16.1 counter, the Counters 16.1, 16.2 determine the time during which the requirement for the exchange of CS should be processed by the channel. At the same time, the signal from the output of 66.1 elements And 12.1 is fed to the inputs of blocks 4.1 and 4.2. In block 4.1, this signal is fed to the input element And 80, and in block

4.2- at the input of the element I 82, t, e, depending on which subscriber is selected in the US, the trigger 84 of block 4.1 or the trigger 86 of block 4.2 will appear in one state. Accordingly, the element 80 of block 4.1 will turn out to be open. or element And 82 block 4.2. If the element 80 is open, the signal from its output will set the trigger 74 to one state, the zero-jth state will trigger 87 and 84, if the And 82 element of the 4.2 block is open, the signal from its output will set to unity state trigger 76, to the zero state - triggers 86 and 87, Resolving signal from trigger output 74 through output 50.1 of the block

4.1 enters unit 5 of the block 5 on the elements AND 101, 103.105, 107, 111 and 117, thereby logically connecting the first subscriber to the first channel. After decrypting the command on the decoder 8.1, the actual exchange of information between the channel and the subscriber begins, similarly to the prototype. At the end of the exchange cycle, the generator 138 generates the last clock pulse, which initializes the elements of block 3.1 and, from the output 42 of this block, through the open element AND 107 element OR 116, output 33 of unit 5 enters unit 4.1 for installation in

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the zero state of the 7A and 76 flip-flops. If the trigger 76 of the block 4.2 is set to one, then the signal from its output through the output 52 and 2 of the block 4.2 goes to block 5 on the elements AND 126,128, 130,122,124З133, logically connected thus the second subscriber to the first channel. Then the exchange process proceeds as described, with the only difference that at the end of the exchange cycle the signal from 46 and 3.2 of the block 3.2 comes through an open element AND 122, element OR 132, output 34 of block 5 into block 4 , 2 ,, on the installation of the initial state of the t-riggers 74 and 76 tion of the first embodiment mode.

If for a given time the channel did not respond to the TRB-A signal, i.e. if the command and signal are not sent, then after a predetermined time has elapsed, the counter 16.1 overflows and at its output 72.1 an overflow signal appears, which sets the trigger 11.1 through the element 1LI. At the same time, this signal enters block 4, Once, the source state is set via the OR 93 element, the trigger 84 s is the single state trigger 81, if the trigger 87 is in the zero state through the AND 100 element, the trigger 81 is reset to the initial state by the same signal.

The signal from the output 72.1 of the counter 16.1 is also fed to the inputs of the elements And 88s 98 of the block 4.1, however in this mode of operation these em: the elements are closed, In block 4.2 the signal from the output 72.1 of the counter 16, 1 is coming. to the input of element 95, however, in this mode this element is closed; no action is taken. Thus, after a predetermined time has elapsed, the unserved by the channel is set to the initial state,

In the second variant of the first 5-mA decision, the channel sends the second modification, the address code, to the RS. As a result of decoding the address code at the output, for example, 68.1 the address control signal appears, which goes to block 6 the input element And 152, If the inputs of the block 6 simultaneously receive signals from the outputs 68.1 and 68.2 of the decoder 7 "1 and 7.2, respectively (this means

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at the same time, two channels initiate the exchange of information with two subscribers), then the right to organize communication with two subscribers receives a channel that currently has the highest priority. The priority value is set by the position of the switch P of block 2, respectively, the priority signal of the sample is in accordance with one of the codes 62 or 63 of block 6, then this signal, for example from output 62, goes to block 4.1 to the input of the element lilM 83 and simultaneously to block 4 , 2 to the input element And 99; Thus, the channel intends to connect two subscribers at the same time,

The signal from the output of the element {SHI 83 passes according to the scheme in accordance with the state of the elements of the US, as was described for the first variant. On the VGZGKOD element AND 99 of the block 4.2, the signal is only in the event that, in this Mot-jeHT, the second channel does not work with its second subscriber, that is, if the trigger 84 of the block 4-2 is in the zero state. If the trigger 84 of the block 4.2 is in the zero state, then the AND 99 element is open, and the priority sampling signal from the output 62 of the block 6 passes through this element, through the OR 89 element and sets the trigger 86 to the single state. At the same time, the signal from the output of the element OR 89 goes to the output 49.2 of the block 4 22 and then to the input of the element OR 13.1, After the trigger Γ is set (, 1 in a single state, the operation of the AC occurs as described above.

The second mode of operation of the CS is the exchange of information between the channel and the subscriber on the initiative of the subscriber

} In this case, the subscriber sets the Signal Exchange Request (TO) signal, which sets the trigger 148 of the communication unit 3 with the subscriber to one state. Then, from the output, for example, measures 44, of the 3v1 block, the TO signal enters the 4.1 block at the input of the element And 91, The element And 91 turns out to be open if at that moment no one of the channels organizes exchange with this subscriber, those. the trigger 84 of block 4.1, the trigger 86 of block 4-2 and the trigger 156, 161 of block 6 are in the zero state with

The signal from the output element And 91 sets the trigger 87 in one state. A single signal that appeared at the output of the trigger 87 sets the trigger 84 through the element OR 93 to a single state. At the same time, the signal from the output of the element OR 93 through the output 54.1 goes to the reset of the flip-flops 156, 161 of unit 6 and the setting to single state of the spitere element OR 13.1 trigger 11.1. If, in response to the channel-generated TRB-A signal generated by the trigger 11.1, the command and the VBR-K signal is sent, then the CSS operation proceeds as described. If the channel does not send a command and a VBR-K signal to the CS during the specified time, the overflow signal from the output 72.1 of the counter 16.1 sets the trigger 11.1 to the zero state. Simultaneous output signal

72.1 enters the block 4.2 at the input of the element And 95, but at the moment

this element is closed, and in block 4o1j where the trigger is set to one state 81, and the trigger 81 is not reset, since the elements 100 and 75 are closed. Further, the signal from the output 72.1 sets the trigger 84 to the zero state and enters the input of the AND element 98 of the block 4.1. Element And 98 turns out to be open if the trigger 87 in the unit state of the trigger block 87 and the second channel does not work with any subscriber, i.e. the trigger 84 of the block 4.2 and the trigger 86 of the block 4.1 are in the zero state. Then the signal from the output of the element AND 98 through the element OR 89 sets the trigger 86 to the one state and through the output 49.1 enters the input of the element OR 13.2, thereby setting the trigger 11.2 to the single state. If the second channel turns out to be a busy exchange with the second subscriber, then the AND element of the 88 block 4.1 is open, and the signal from the output 72.1, passed through this AND element, will set the trigger 87 to the initial state 1, so in this case the exchange did not take place the MS circuits are reset. After installing the trigger

11.2. In a single state, the signal from its output 65.2 through the corresponding amplifier of the communication unit 1.2 with the channel enters the second channel. AT

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The channel sends the response to this signal to the CSS command and the signal of the VBR-K, with their arrival, the CSS circuits work in the same way as described. If the second channel does not send a command and a VBR-K signal to the CS during a specified time, then an overflow signal from the output. 72.2 counter 16.2 will set the trigger 11.2 through the OR element 14.2 to the initial state. At the same time, this signal enters blocks 4.1 and 4.2. In block 4.1, it arrives at the input of the element AND 95, which is open, since the triggers 81 and 87 are in a single state. The signal from the output of the AND element 95 sets the triggers 81, 87 and 86 to the zero state. Thus, since neither the first nor the second channels responded to the subscriber's demand, the US circuits are reset.

In block 4.2, the signal from output 72.2 sets the trigger 81 to one state and then to zero through the open element AND 75 (since the trigger 81 of the block 4.1 is still in the one state at that time) and the element OR 85. The element 100 also at this time the moment is closed, since the trigger 87 of block 4.2 is in the zero state. Both the 88 and 98 elements are closed, since the trigger 84 of block 4.1 and the trigger 87 of block 4.2 are in the zero state. Through the element OR 94, the trigger 84 is set to the zero state (confirms), since all the US circuits operate to service the TO signal from the subscriber, such a confirmation reset of the trigger 84 does not interfere with the operation. The operation of the CSS when an incoming signal is received from the second subscriber is anaphodic.

Claims (2)

1. A device for interfacing an I / O channel with subscribers, containing two communication units with a channel whose input / output groups are the corresponding input / output devices of the device for connecting i information and control I / O to the first and second I / O channels , switching unit connected respectively to the first and second groups of outputs with the first groups of inputs of the first and second units of communication with the channel, and the first group of information I / O with the first group of the first communication unit with subscribers, the second group of inputs and outputs of which is a group of inputs and outputs of the device for connection to the information and control groups of subscribers I / O of the first groups, six groups of AND elements, two command decoders, two address decoders, two triggers, two AND elements, two OR elements, a mode setting unit and the first sample control block, the first and second outputs of which are connected to the first address group in the first and second inputs of the switch unit and the request input, respectively, to the outputs of the first and second And elements and the output of the first communication unit with subscribers, the group of outputs of the first communication unit with the channel is connected to the first inputs of And elements of the first, second and third groups, the second inputs of which are connected respectively to the first, second and third outputs of the first communication unit with the channel, and the outputs respectively to the input groups of the first address divertor, first command decoder and the first group of information inputs of the ko block the first and second information inputs of the first command decoder connected to the group of outputs, the group of outputs of the second communication unit with the channel is connected to the inputs of elements AND of the fourth, fifth, and other lines, the second inputs of which are connected respectively to the first, second and the third output of the second communication unit with the channel, and the group of outputs -. respectively with the input groups of the second address decoder, the second command decoder and the second group of information inputs of the switching unit, the third and fourth information inputs connected to the output group of the second command decoder outputs of the first and second OR elements are respectively connected to the installation inputs of the first and second triggers, outputs connected respectively with the first inputs of the first and second elements And and the signal inputs of the demand of subscribers of the first and second communication units with the channel, solid outputs of which are connected respectively to the second input five 0 five 0 five 0 five 0 The first and second elements And, the input of the sample signal of the first communication unit with the channel is connected to the third output of the first sampling control unit, characterized in that, in order to increase the throughput of the device, two counters, two elements And two elements are entered into it OR, priority block, time stamp generator, second sampling control block and second communication block with subscribers, with the second group of information inputs / outputs of the switching block connected to the first input / output group of the Second communication block with subscribers, watts The group of inputs and outputs of which is a group of inputs and outputs of the device for connecting to the groups of information and control inputs and outputs of subscribers of the second group, and the output is connected to the request input of the second sampling control unit, the group of inputs and outputs of which are connected respectively to groups of outputs and inputs of the first sampling control unit, and the first and second outputs to the second group of address inputs of the switching unit, the third and fourth outputs of which are connected respectively to the reset inputs of the first and second blocks The fetches of the sampling control, the first and second inputs of time signals of which are connected respectively to the outputs of the second and first counters and to the second and first inputs of the first sampling control unit, the third output of the second sampling control unit is connected to the input of the sampling signal of the second communication unit with the channel, and the first and the second sample inputs — respectively, with the outputs of the second and first elements AND; the fourth outputs and the synchronization inputs of the address of the first and second sample control blocks are connected respectively to the first inputs and the second and first OR elements and the first outputs of the first and second address decoders, the second outputs connected respectively to the first and second resolution inputs of the priority block, the input group of the priority setting of which is connected to the output group of the mode setting block, and the first and second request inputs are respectively the second inputs of the first and second elements OR ten 151425696 The first and second sample control inputs, the first, the resolution inputs and the syntax input of which are connected respectively to the first, second and priority outputs of the priority block, time stamp remover, the first inputs of the third and second elements, and the second inputs of which are connected to the outputs of the first and second and the counting inputs of the first counters, the inputs of the first and second elements of the first and second elements OR, respectively, connected to the first and second counters of the first and second elements, respectively, with the outputs of the first and second ovs. venno igger 15 one m r ti and ti ed dv hto hgo i n that h according to m not mr m i v ve ve and ch ora on the second day Ish and we are you 2. The device according to claim 1, wherein the sampling control block contains six triggers, fourteen AND elements and eight OR elements, with the outputs of the first OR element, the first and second triggers, respectively the third, second and first block outputs, the input of the first element I is the first input of the block time signals, the first inputs of the second, third and fourth elements AND are connected to the output of the second OR element, the first and second inputs of which are respectively the first input the resolution and the synchronization input of the block address, the first inputs from the fifth to the ninth elements And are connected respectively to the first and second inputs of the block selection, the first input of the time signals of the block, the synchronization input of the block and the code of the third trigger, inverse outputs of the fourth and fifth triggers connected respectively to the second inputs of the ninth and fourth elements AND, the outputs of the third to the eighth elements OR are connected respectively to the reset input of the third trigger, the installation inputs and the reset of the fifth trigger, the reset input and sixth inputs of the flip-flop setting and resetting the fourth flip-flop, the output of a tenth AND gate is coupled to a first input of the fourth OR gate, the first and second inputs 0 0 five 0 five five 0 five 0 five the eleventh element AND is connected respectively to the output of the second element OR and to the direct output of the fifth trigger and the second inputs of the third and sixth elements AND, the second and third inputs of the fourth element OR are connected respectively to the outputs of the twelfth and thirteenth elements AND, the first inputs of the twelfth and fourteenth elements And the eighth element OR is connected to the first input of the time signals of the block, the first inputs of the tenth and thirteenth elements I are connected to the inverse output of the fourth trigger, the direct output on connected to the second input of the fifth element AND, the output of which is connected to the installation input of the first trigger, the second input of the eighth element AND, and the first input of the sixth element OR, from the second to the fourth inputs of which are connected with the outputs of the seventh, sixth and ninth AND , the direct output of the sixth trigger is connected to the second inputs of the second, ninth and twelfth elements AND and the first input of the seventh OR element, the second input of which and the first and second inputs of the first OR element are connected respectively to the output Dami fourth, third and second elements And the third input of the fourth element And is connected to the inverse output of the sixth trigger and the second input of the fourteenth trigger, the output connected to the first input of the third element OR, the second and third inputs of which are connected to the outputs of the first and nine elements And the first and second inputs of the fifth element OR are connected respectively to the outputs of the sixth and ninth elements AND, the reset inputs of the first and second triggers are connected to the reset input of the unit, the installation input of the third trigger and the third input of the ninth element And are connected respectively to the first and second inputs of the time signals; the outputs of the fourth and seventh ICH elements are the fourth and fifth outputs of the block, respectively; The inputs of the second and sixth flip-flops are connected respectively to the outputs of the sixth and eighth And elements, the third input of which is the block's input input, the third inputs of the second and twelfth And elements, 1714 the third input of the third element H connected to the second input of the seventh And element, the fourth input of the eighth And element, the second inputs of the first, tenth And element form a group of block inputs, the second input of the thirteenth element And is the second input of the block resolution, third output the first trigger, the fourth output of the fourth trigger, the inverse output of the fifth trigger, connected to the fourth output of the twelfth element, the inverse output of the fourth trigger, the direct output of the sixth trigger, and the output of the eleventh element, And a group of outputs of the block. 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