SU845155A1 - Device for interfacing processor with input-output units - Google Patents

Description

one

The image is in the field of computer technology and can be used, for example, in aggregate information acquisition and processing systems and control computer systems.

Devices are known for interfacing a digital computer with external devices fl, comprising; communication register, analysis block, address block, address modification block, control word register, additional control word register and buffer block,

The disadvantage of these devices lies in the limited field of application, since they provide the implementation of a rigidly specified exchange protocol and do not allow the interface of input-output devices having different protocols.

The closest to the invention in its essence is a universal interface of the central and peripheral systems (2), which contains the decryption unit of the central system commands, the central system data receiving unit, the central system data transmission unit, the interrupt signal generation unit, the output information buffer, output control buffer, input information buffer, input control buffer, group control blocks. The output of the central system data reception unit is connected to the input information output buffer, to the first data input of the output control buffer, to the input control input buffer, to the input information input buffer, and to the input of the mode code of the interrupt signal formation unit. The input of the code entry of the mode of the formation of the signal of interruption is connected to the third output of the decryption unit of the commands of the central system and to the inputs of the entry of the code of the mode of the buffers for information and control. The outputs of the input information and control buffers are connected respectively to the first and second data inputs of the central system data transfer unit. The read input of the data transmission unit of the center of the PC system is connected to the fourth output of the command decryption unit of the central system. The first and second outputs of the decryption block of the central system commands are connected respectively to the write input of the output information buffer and to the data input input of the output control buffer 2.

The disadvantage of this device lies in its limited scope due to the fact that it uses only control signals of a predetermined form and only pulse acknowledgment from input / output devices, as well as resetting of confirmation signals of only certain output control signals.

In addition, the need for large amounts of CPU time to control the device during the input-output of each byte of information reduces the overall system performance.

The aim of the invention is to expand the field of application of the device.

The goal is achieved by the fact that the device containing the receive block, data block, data transfer block, processor decryption block, interrupt signal generating block, output and input information and control registers, the output of the data receive block connected to the input of the mode code of the block generating the interrupt signal, the input data of the input and output information registers and the input control register and the first data input of the output control register, the first and second outputs of the coma decoding unit The processor's nDs are connected respectively to the data write inputs of the output information and control registers, the third output is connected to the write inputs of the mode code of the interrupt signal shaping unit and the input control and information registers, and the fourth output to the read input of the data transfer unit, the first and second inputs the data of which are connected respectively to the outputs of the input information and control registers, a block for generating the output feedback code and a block for analyzing the input feedback code are entered. The data output and the output of the data tracking signal generation unit of the output feedback code are connected respectively to the second data input and the write input of the feedback control code of the output control register. The input of the return code sample is: in write and read, write to the mode code and the entry of the setting code entry is connected respectively to the first, fourth, third and fifth outputs of the processor instruction decryption unit, the data input is connected to the output of the data reception unit, and the input of the readiness feedback code sample is input to fixing the data of the input control of the information register, the input

the settings of the interrupt signal generating unit, the readiness input of the data transmission unit and the output of the input feedback code analysis unit. The inputs for recording the mode code, tuning code and reset input are connected to the third, fifth and sixth outputs of the processor decryption block, respectively, the data input to the output, the data receiving unit, and the reverse communication code input to the output of the input control register. The input feedback code analysis block contains a mask register address decoder, the first input of which is connected to the input of the block setup code entry, the second input to the block data input and ne; the first to fourth register registers of the mask and the enable enable trigger, and the outputs from the second inputs of the respective mask registers, the outputs of which are connected to the first inputs of the elements AND of the group, the second inputs connected to the feedback input and the inputs of the elements of the PE group, the third inputs to the outputs of the elements NOT of the group, but the outputs - with the corresponding inputs of the OR element, the output of which is connected to the first input of the AND element, the second input of the ready resolution enable trigger, the second input of which is the recording of the mode code, and the output to the first input of the ready trigger, the second input and output which are respectively a reset input and a block output. The feedback code generation unit contains six control registers, the first inputs of which are connected to the corresponding outputs of the control register decoder, the first input connected to the input of the unit setup code, and the second to the data input of the block, the second trigger inputs enable control by writing, by reading and by readiness, the second inputs of which are connected to the write input of the code for the block mode and the outputs respectively to the first inputs of the first, second and third elements AND, the outputs connected to the corresponding inputs of the OR element, the output of which is the output of the accompanying data. The outputs of the first and second control registers are connected to the first inputs of the corresponding AND elements of the first group, the second inputs connected to the second input of the first element AND, and the sample input of the feedback code when the block is written. The output of the third and fourth control registers are connected to the first inputs of the corresponding elements And the second group, the second

inputs connected to the second input of the second element And the input sample code feedback when reading the block. The outputs of the fifth and sixth control registers are connected to the first inputs of the corresponding AND elements of the third group, the second inputs of which are connected to the second input of the third And element and through the pulse shaper to the input of the feedback code on the readiness of the block. The outputs of the elements of the first and third groups are connected to the corresponding inputs of the elements of the OR group whose outputs are the output of the data block.

Figure 1 shows the structural diagram of the device; Fig.2-8 - functional block diagrams of the device.

The device contains a processor command de-blocking unit 1, a data receiving unit 2, an interrupt signal generating unit 3, output 4 and input 5 information registers, an input feedback code analysis unit 6, a feedback generating code generating unit 7, a feedback data transmission unit 8 , output 9 and input 10 control registers.

The processor instruction decryption unit 1 (Fig. 2) contains a conjuncer 11 (element I) of receiving a write command (2I), a conjunctor 12 receiving a read command (2I), a decoder 13 of a two-input address, KOHbiOHKTOp 14 commands for recording information (2I), a conjunctor 15 control write commands (2I), conjuncer 16 write commands (2i), conjuncer 17 write setting commands (2I), block of conjunctors 18 read commands (3 x 2I), first 19, second 20, third 21, fourth 22, fifth 23. and the sixth 24 block outputs.

The data transmission unit 8 contains a block of conjunctors (elements and) 25 of the transfer of the information code (8 X 2I), a block of conjunctors 26 of the transfer of the control code (8 x 2I), a conjugator of 27 readiness transfer (2I), a block of disjointrs (OR elements) 28 of the transmission data to the processor (7 X 2I), disjunctor (OR element) 29 transfer readiness to the processor (3 or), first 30 and second 31 data inputs of the block, input 32 of the readiness of the block AND, input 33 of the read block.

FIG. 4 shows one of the possible implementations of an interrupt signal generating unit comprising an interrupt enable conjugator 34, an interrupt enable trigger 35, a block setup input 36, a block mode code input 37, a block mode code entry input 38.

FIG. 5 shows an example of the implementation of the input information register (buffer) 5, which includes the receiver register 39 information, the fix resolution trigger 40, the HE element 41

fixation, disjunctor 42 fixation

(2 OR), input 43 block data, input.

44 block mode code entries, input

45fixing block data and output

46 block.

FIG. 6 shows the implementation of the input control register (buffer) 10 containing {Register 47 receiver control, trigger fixation trigger 48, fix element NOT 49, fixation disjunctor 50

0 | (2ILI), block data input 51, block mode code entry 52, data blocking input 53, and block output 54.

The unit 6 for analyzing the input feedback code (Fig. 7) contains mask registers 55-58, a group NOT element 59, AND elements (conjunctors) 60 groups (16 X 2I), (disjunctor) readiness element OR 61 readiness formation (16 or ), element (conjunctor) 62

0 readiness enable (2I), readiness trigger 63, decoder 64 of mask register address, readiness enable trigger 65, block feedback code input 66, block data input 67, block setup code entry input 68, block mode code entry output, block reset input 70 and block readiness output 71.

The feedback output code generation unit 7 (FIG. 8) contains control registers 72-77, AND elements (conjunctors) 7B, 79, and 80 of the first, second, and third groups, and OR elements (disjunctors) 81 of the automatic control code group ( 8x3 OR), the address register decoder 82, the driver of 83 readiness pulses, the control resolution trigger 84 io write, the trigger 85

0 read control permissions, read control permission trigger 86, AND control elements (conjunctors) 87-89 write control permissions (2I) on read (2i), and readiness (2I), OR element (disiniter 5) 90 automatic recording control code (3 OR), block data entry 91, block setup code entry entry 92, block mode code entry entry 93, sampling input 94

0 feedback code on the readiness of the block, input 95 sample feedback code when reading a block, input 96 sampling feedback code when writing a block, output 97 data

5 blocks and 90 output of block data.

The data reception unit 2 from the processor is a block of standard bus drivers, the data transfer unit 8 to the processor is a switching controlled circuit, connecting 1: 1 to one of its three information inputs to its output, depending on the controls. sig5 nal.

The unit 1 for decrypting the commands of the central system is designed to receive the instructions of the processor and form on it the internal control commands of the device.

The data receiving unit 2 couples the output bus of the processor to the internal data bus of the device. The data coming from the processor, depending on the accompanying write commands, are intended either to set the required device operation modes / or to Block the device’s blocks for a given information exchange algorithm with a given input / output device (WU) or to transfer it to the slave unit. .

The data transmission unit 8 of the central system is designed to transmit data to the processor by reading commands received from the slave or generated inside the interface device. The interrupt signal generating unit 3 is designed to generate an interrupt signal informing the processor that the interface device is ready to continue the exchange of information with the slave. In registers (buffers) 4 and 9, two groups of independent parallel data transmission channels in slaves are formed. The size of these registers is determined by the number of data bus lines. Buffer 4, unlike buffer 9, has two data inputs and, respectively, two input and output records, i.e. In addition to the data storage function, the buffer 9 performs the function of multiplexing data arriving at its first or second input. Two input registers (buffers) information 5 and control 10 Form two groups of independent parallel channels for receiving data of a slave. Both registers perform the functions and data storage and have a width equal to the size of the output register of the device. The input registers also contain control circuits that allow, depending on the mode code recorded in them, to independently allow or prohibit the data capture function in these registers.

The outputs of these registers are connected to the corresponding inputs of the data transmission unit 8. The output of the ID register is also associated with the input of the feedback code of the block b of the analysis of the input feedback code for performing the function of universal autonomous control of the slave. The unit 6 for analyzing the input feedback code is designed to determine the moment on which the given output control channels of the slave, arriving at the register 10, of signals of a given shape, which form a certain input feedback code. At the moment of generating a given code, the ready signal is generated at the output of this block, ensuring the closure of the internal feedback, realizing the universal autonomous control function and performing a number of other independent internal control functions. The feedback code generation unit 7 is designed to generate a data code at its output, determined by signals received at its sample inputs, and to generate a signal at the output of a tracking signal for rewriting these codes into an output control register.

The device works as follows.

In the initial state, all internal autonomous functions of the device are prohibited.

From the point of view of the processor, the device is two independently to the address of the first output registers 4 and 9 and two input registers 5 and 10.

By writing data to the register 4 or 9, the data received from the processor through block 2 is stored in one of the indicated registers with the help of signals received at their data recording inputs. The data reading commands received at the input of the reading unit 2, information removed from register 5 or 10, depending on the address specified in the command, enters the processor.

The functions of capturing data in registers 5 and 10, internal autonomous control functions, and the interrupt function are not used. This mode is identical to the On mode of the prototype.

The main mode of operation of the device is the mode using the functions performed by blocks b and 7, providing the mode of universal autonomous control of the slave.

The commands for writing the mode code blocks 6 and 7 are included in the operation. Mode codes arrive at the data inputs, independently allowing or disallowing the formation of the ready signal (GT) of block 6 and any of the feedback code samples from the corresponding input sample commands in block 7.

Before the exchange of information begins, blocks 6 and 7 are programmatically tuned to a predetermined WU control algorithm by writing to them using the corresponding commands to write tuning codes that arrive on the input data buses of these blocks. Moreover, the setting of the mode and the setting up of the device are carried out only once, after which the exchange is performed on just one command to read or write information.

 Upon a command to write data to the information byte transferred from the processor, it is placed in register 4. At the same time, the same command is used to select the slave request control byte from block 7. Thereafter, the processor is released from the maintenance of the device.

According to the request code, the VU is put into operation, read the information byte recorded in register 4. After completing the work cycle, the VU exposes a confirmation code that appears at the output of input register 10 and then at the input of the feedback code of block 6, at the output of which signal readiness GT.

On this signal, in block 7, a new feedback code is transmitted, sent to register 9, the request is automatically removed, and / or a new one is set if necessary.

At the same time, the ready signal G arrives in registers 5 and 10, fixed by the incoming data from the slave, if the corresponding functions implemented in these registers are allowed by mode codes. In addition, the readiness signal is fed to the input of the GT block 8 to block 3. The latter generates an interrupt signal on the input control panel of the processor, if this function is enabled by a mode code previously recorded in the block,

The processor learns that the device is ready either programmatically (by analyzing the GT signal using the GT read command) or via the interrupt mechanism. Having received readiness, the processor issues the following write command to the devices, passing the blackened information byte.

The reading of data from the processor to the processor occurs in the following sequence. WU exposes the next information byte arriving in register 5, and, after one or several input control buses, the request code entering register 10. The request code from the output of this register goes to the input of the feedback code of unit 6. At the moment of appearance The required code at the output of this block generates a GT ready signal, performing the same functions as for recording information.

From block 7, the feedback code is selected and written into the output control register, together with the VU when the device is occupied. Considering the readiness signal from the device in one of the previously mentioned ways, the processor issues a read command that transfers data received from the block 8 - from register 5. At the same time, from block 7 a new code is selected that goes to register 9 to indicate the release I / O device devices for receiving the next informational byte.

Input, reset of block 6 is used to reset the set internal ready signal after the processor has received it. A reset is performed on each read command to write data from the device.

The described structure of reading and writing data transmitted through the interface device is the most typical for the majority of slaves, but not the only one possible for this device.

In particular, always regardless

By using this function, you can write any code to register 9 or read the code stored in register 10 without changing the device's modes of operation.

Luba of the internal managers

15 functions of the data latching function in registers 5 and 10, the function of sampling the feedback code from block 7 and the interrupt function can be enabled or disabled regardless of others.

It is important to note the differences, which are not fundamental in nature, between this device and the prototype device.

The prototype implements three modes.

5, and in the first two modes it is possible to control the direction of the inclusion of registers of group A and group B.

However, for most slaves, the byte data transfer format

0, the common configuration of the interface device is a configuration holding one parallel eight-bit output register, one parallel eight-bit input

5 register for data exchange and a set of input and output control channels containing from 2 to 16 lines.

 Therefore, the configuration of this device is fixed: registers 4 and

0 9 always give data to the control unit, and registers 5 and 10 always receive data from the control unit. All registers have the same bit depth.

As a result, a wide range of operating modes is possible in the device.

5 overlapping all possible modes of the prototype (except for the bidirectional mode), as well as creating new opportunities for controlling a wide class of high-voltage devices.

0

The introduced software-adjustable blocks, the block of input code analysis for feedback 6, and the block for generating the output code for feedback 7 make the control mode of the device universal.

In the proposed device is implemented internally, autonomously, multichannel with cross-switching of control function channels.

The unit for analyzing the output code of the feedback link, which is pre-programmatically adjusted to a given code, allows you to record the time of the appearance of a certain signal front on one or several input signals.

input control register channels. In this case, both the polarity of the fronts themselves and the channel numbers are independently controlled.

The feedback code generation unit 7, in one of the input signals of the sample, sets in register 9 any (predetermined) code, thereby forming any level on any output control channel. As a result, a universal internal multichannel cross-switched channel control of the slave is realized autonomously (without the processor).

The blocks of the device are as follows.

Conjunctors 11 receiving a write command and 12 receiving a read command from block 1 are designed to receive from the control bus of the processor the write and read signals addressed to this ycTpoftcTBy. The decoder 13 serves to decipher the two lines of the processor’s address bus and to control the write commands 14-17 and the read command conjunctors 18. At the write command that is addressed to this device, the address set at the input of the decoder 13 opens only one of the conjunctors. As a result, the recording signal from the output of the conjuncer 11 passes to the output of only one of these conjunctors, forming only one and the internal recording signals; recording information, recording management, recording mode, or recording settings. According to the information recording signal taken from the output of block 19, the information eight-bit i code from the internal bus is written to register 4. By the control recording signal taken from output 20, this code is written to register 9. By the recording signal of the mode taken from output 21 the block, the values of the individual bits of the code installed on the data bus are recorded in the corresponding resolution triggers of blocks 3,5,6 and 7. By the signal of the tuning record taken from the output 23 of block 1, the values of the four small bits of the data bus code are recorded and one of the four mask registers of block 6 or one of the six control registers of block 7. In this case, the higher bits (four) of the data bus code are used to address one of these ten registers. The write command also, regardless of the value of the address at the output of the decoder 13, generates at the output 24 of block 1 a reset readiness trigger signal in block b. Upon a reading command addressed to this device, a read signal appears in the second input of the block 18 of conjunctors of reading commands.

Block 18 consists of three AND elements controlled from the output of the decoder 13. The output of block 18 can generate three read signals: read information, read control and read readiness, defined by three address values: information addresses, control addresses and readiness addresses, respectively . The read signal from the output 22 of block 1, defined by the address information, control or readiness, controls the transfer to the processor or the information code from the register 39, or the control code from the register 47, or the readiness code from the ready trigger 63 information or by a read signal, determined by the address of the information, a sample is taken from block 7 of the corresponding control code and written to register 9.

Blocks 25 and 26 of the elements And (conjunctors) of the transmission of the control code of the block 8 are intended to transmit information or control chips to the processor from the VU, respectively. A readiness transfer conjugator 27 is designed to transmit to the processor a ready signal generated inside the device (in block 6) using the control code. The transmissions through the indicated blocks 25, 26 and 27 are synchronized by the read control signals taken from the read input 33 of block 8. By the read signal determined by the information address or the control address, an eight-bit information code inputted to input 30 or an eight-bit control code arriving at input 31, passes through blocks 25 or 26, respectively. Moreover, the lower 7 bits of the information or control codes arrive at a block of 28 disjointrs, and the high eighth bit goes to a disjunctor 29, at one of the inputs of which a readiness signal is received, synchronized on the conjunctor 27 by a read signal determined by the readiness address.

Trigger. 35, the interrupt enablement of the block 3 is intended for storing a one-bit indication of permitting the generation of an interrupt request to the processor. If the trigger 35 is in the single state, the conjugator 34 times the interrupt rate skips the ready signal, removed from the input 38 of the unit installation. If this trigger is in the zero state, the connector 34 is closed and the ready signal is blocked. The permission indication is written to the trigger 35 from a certain bit of the data bus, which enters the input 36 of the mode code, at the write signal

mode, the input to the record 37 Coy mode. . Structurally, registers 5 and 10 are identical. Informational

39 and control 47 registers of the receiver are used to receive and store codes from the WU, information and control, respectively. The resolution triggers 40 and 48, the HE elements 41 and 49 and the fixation disjunctors 42 and 50 are designed to control latching on the readiness signal of the data in registers 39 and 47, respectively. Signs of the resolution of fixing (or latching) are recorded in the triggers

40 and 48 from certain bits of the data bus arriving at inputs 45 and 51, according to the mode recording signal received at inputs 44 and 52 of the recording of mode codes, respectively. Single signals at the outputs of the flip-flops through the corresponding disjointrs arrive at the inputs of the registers, disabling the latching function. If at the outputs of the resolution triggers are zero signals, the signal values

on; inputs of registers 39 and 47 are determined by a ready signal supplied to inputs 45 and 53 of data latching, respectively. At the moment of the readiness signal transition from zero to one, a zero signal is set at the inputs of the registers, fixing the data stored in these registers.

Unit 6 includes a memory for storing the mask code, a masking scheme for direct and inverse values of the feedback code bits, and a scheme for generating the output readiness signal. The four four-bit mask registers 55-58 are designed to store the 16-bit mask code controlling the masking elements AND 60. Codes in registers are written to the four lower data bus bits taken from data input 67. In this case, the upper four bits of the code, taken from the same input, are fed to the second input of the decoder 64, intended to indicate the number of the register to which the code is written. The writing to the registers is synchronized with the setting recording signal coming from the input 68. The masking scheme is performed on the elements and 60 and the OR-61 element. The output of which passes the disjunctions of those direct or inverse values of bits taken from input 66 and from the output of elements NOT 59, which correspond to unit values of bits of the mask code.

The readiness output signal generating circuit includes a trigger 63 and a read permission enable element 62. To fix the moment of readiness, i.e. A locked feedback code can be used; a standard trigger with a: sync recording input. The output of the element And 62 in this case must be connected to the sync input of the trigger.

With a single value of the trigger output signal, the signal from the output of the disjunctor 61 passes through the conjunctor 62 and is stored in the trigger 63, otherwise this

0, the signal is blocked, and therefore, a readiness signal is not generated at the output 71 of readiness of block 6. The permission sign is written to the flip-flop 65 from a certain bit of data bus to the input 67 of the block, according to the recording signal of the mode entering the recording 69 of the mode code. The flip-flop 63 is reset on a signal from the block reset input 70.

0

Block 7 contains a memory for storing feedback output codes (control codes transmitted to register 9), a sampling circuit from this memory, and a signal shaping circuit for writing this data to register 9. Three pairs of four-bit control registers 72-77 form three registers for storing eight-bit control codes when writing, when reading, and when ready, respectively. Codes in these registers are written to the four lower data bus bits taken from data input 91. In this case, the top four bits of the bus, taken from this input, go to the second input of the decoder 82, intended to indicate the number of the register to which the code is written. The writing to the registers is synchronized by the setting write signal coming from the input 22 to the decoder.

The data sampling scheme is performed on three groups of elements AND 78-80 and elements OR 81. When the inputs of elements 78 and 80 are fed to the inputs, samples are taken from inputs 95 and 96 and s from the output of the driver 83 at the outputs of these elements And and at output 97 to control codes for write, read, or readiness, respectively. Moreover, the shaper 83 serves to generate a short pulse according to the readiness signal received from the input 94 of the Sample feedback code on the readiness of the block.

The recording signal shaping circuit in ce6rf includes the element OR 90. And 87, 88 and 89 elements and three flip-flops 84, 85 and 86. With single values of the output signals of these flip-flops, the signals coming from the inputs 96.95 and from the output of the former 83, pass t through elements 87, 88 and 89 and form at the output of the element OR 90 and at output 98 a signal for writing the feedback code to the register 9. At zero input trigger signals, the formation of a signal at block output 98 is blocked. Permission indications are recorded in the 84.85 and 86 triggers of certain data bus bits received at input 91.

Thus, the field of application of the device is expanded by providing the ability to adjust the interfering with specific VU connected to this device. In this case, compared with the prototype, the device has a higher speed.

Claims (3)

1. A device for interfacing a processor with input / output devices, comprising a data receiving unit, a data transmission unit, a decryption unit, processor commands, an interrupt signal generating unit, output and input information and control registers, the output of the data receiving unit being connected to the input the mode code of the interrupt signal generation unit, the data inputs of the input and output information registers and the input control register, and the first data input of the output control register, the first and second outputs of the block Encryption of processor commands is connected respectively to the data write inputs of the output information and control registers, the third input to the write inputs of the code of the mode of the interrupt signal generation unit and the input control and information registers, and the fourth output to the read input of the data transmission unit, the first and second the data inputs of which are connected respectively to the outputs of the input information and control registers, different from the fact that, in order to expand the field of application of the device, it is entered into it to form the output feedback code and the input feedback code analysis unit, the data output and the output of the data tracking signal of the feedback output code generation unit are connected respectively to the second data input and the feedback recording code entry of the output control register, inputs sampling the feedback code when writing and reading, the entry of the entry of the mode code and the entry of the entry of the setup code, respectively with the first, fourth, third and fifth outputs of the decoding unit of the processor commands, the data input with Exit block receiving active and sample output feedback preparedness stroke - to the inputs fixing the data of the input control and information registers, the input. The settings of the interrupt signal shaping unit, the readiness input of the data transmission unit and the output of the anatomization unit of the input feedback code, the inputs for writing the code, the mode, the setup code and the reset input are connected to the third, right and sixth outputs of the processor decryption unit, input. data - to 0 to the output of the data receiving unit, and the input of the feedback code to the output of the input control register. 2. The device according to claim 1, that the unit for analyzing the input feedback code contains the decoder of the mask register address, the first input of which is connected to the input of the block configuration code entry, the second input - to the data input of the block and the first inputs the first 0 of the fourth mask register and the enable enable trigger, and the outputs with the second inputs of the corresponding mask registers, the outputs of which are connected to the first inputs of the AND elements 5 groups, second inputs connected to the feedback input and inputs of the NOT elements of the group, third inputs from the outputs of the NOT elements of the group, and outputs to the corresponding inputs of the OR element whose output is connected to the first input of the AND element, second input connected to the output availability enable trigger, the second input of which is the input 5 records of the mode code, and the output is with the first input of the ready trigger, the second input and output of which are respectively the input of the throw and the output of the block. 0 3. The device according to claim 1, which is based on the fact that the block forming the output feedback code contains six control registers, the first inputs of which are connected to the corresponding outputs 5 decoder control register, the first input connected to the input of the block setup code entry, and the second to the data input of the block, the second inputs of the control registers and 0 first input 1 and trigger control triggers on write, read and ready, the second inputs of which are connected to the input of the record of the mode code of the block, and the outputs respectively 5 but to the first inputs of the first, second and third AND elements, are connected to: the corresponding inputs of the OR element, the output of which is the data tracking output, 0 the outputs of the first and second control registers are connected to the first inputs of the corresponding elements AND of the first group, the second inputs connected to the second input of the first element AND and the input of the feedback code sample during block recording, the outputs of the third and fourth control registers are connected to the first inputs of the corresponding elements AND the second group, the second inputs connected to the second input of the second element AND and the input sample of the feedback code when reading the block, the outputs of the fifth and sixth control registers are connected to rvymi inputs of the corresponding AND gates of the third group, the second inputs of which are connected to the second input of the third AND gate and through the pulse shaper to the entry code sample feedback on the readiness of the block, the outputs of the elements of the first and third groups are connected to the corresponding inputs of the elements of the OR group, the outputs of which are the output of the data of the block. Information sources,. taken into account in the examination 1. USSR author's certificate 404088, class, G 06 F 9/19, 1970. 0 2. Supercomponent computer on one board with programmable input-output interfaces. Electronics, 1976, 3, 28-30 (prototype).