SU1403069A1 - Computer to peripherals interface - Google Patents

Abstract

The invention relates to the field of computing and can be used in systems for collecting and processing information for the exchange between a computer processor and external devices. The purpose of the invention is to expand the scope by providing simultaneous two-way data exchange between the computer and external devices. The device contains a control unit, a request processing unit, a memory unit, two switches, a masking node, a decoder, six registers, a trigger, an OR element. 2 hp f-ly 3 Il. $

Description

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About WITH

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The invention relates to supervisory technology and can be used in information collection and processing systems for the exchange between a computer processor with external devices (WU),

The purpose of the invention is to expand the field of application of the device by providing simultaneous two-way data exchange between the computer and the VU.

FIG. 1 shows a block diagram of the device in FIG. 2 a diagram of a request processing block; in fig. 3 is a control block diagram.

The device contains (Fig. 1) registers 1-6, request processing block 7, control block 8, switches 9 and 10, decoder 11, RSHI element 12, trigger 13, memory block 14 and masking node 15.

Blok 7 (Fig. 2) consists of a shift register 16, groups of elements 17 and 18, a comparison node 19, a decoder 20, a delay element 21, a transmitter 22, a decoder 23, a trigger 24, and an OR 25 element.

Control block 8 includes (Fig. 3) pulse generator 26, elements AND 27-34, elements OR 35-43, trigger 44, delay elements 45-51, triggers 52-54, element 2I-OR 55, shift register 56 and element OR 57.

FIG. 1 also shows groups

device inputs 58-62, device output groups 63-65, device outputs 66 and 67, and device input 68.

The device works as follows.

There are two possible modes of operation of the device, which under certain conditions may overlap in time, the exchange in the direction from the external device to the computer (direction I) and the exchange in the direction from the computer to the control unit (direction II).

Information in direction II is transmitted, if the slave is not occupied, by a request signal from a computer in a non-continuous flow until the occurrence of a code pattern. End of message from a computer. In an exchange in the direction I, the device forms an information message of a certain structure.

Consider the exchange mode in the direction of 1 „

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1. With the aid of an annular shift register 16, controlled by signals from the fifteenth output of control unit 8, a VU is sequentially polled and, if there is a readiness signal for the next VU to be exchanged in the I direction, coming from the VU to the device input group 60, a single output signal a specific element AND 18 of the group through the element OR 25 enters the input of the request processing block 7, initiating the start of the operation of transferring to the device a unit of information from the corresponding slave.

, At the same time, a code combination is formed on the group of outputs of the block 7, which controls the switching of the selected WU with the device. This code combination is fed to the control inputs of the switch 9, which connects to the device the corresponding slave.

2. The output signal of the request of block 7 is fed to the fifth input of block 8. Trigger 52 is set to 1, and the signal at its single output generates control signals at the third, second and nineteenth outputs of block 8, is set

register 6 to 010 ... 00

register 4 to 000 ... 00, as well as allowing reception of information to registers 1-3 from switch 9, to which an address message is received from WU via address 61 and informational 62 inputs of the device.

At the same time, the signal on the unit code of the trigger 52 sets in one state the trigger 44, blocking the pulses from the fifteenth output of block 8 (from generator 26 through element 27) to the ring shift register 16 of the query processing unit 7. Thus, the state of register 16 is fixed until the device completes the operation of receiving a unit of information from the corresponding slave.

At the end of the described operations, the signal from the output of the delay element 45 sets the trigger 52 to the zero state, fixing the state of the indicated circuit elements.

3.C generator 26 through the element 28 and the clock input of the shift register 56 receives the control shift signal. The fourth output of register 56 is set to one, and the signal from the single output of this bit of register 56 is through element I 29, to the second input of which is a single signal from the zero output of trigger 53 set to signal O from the output of element 36 at the end previous cycle of operation of the device simultaneously with. By setting the same signal to state 100,., 00 of register 56, at the fifth output of block 8, a signal arriving at the control input of the decoder 11. In the absence of the specified signal at the control input of the decoder 1 1, its operation is blocked.

The code combination coming from the information outputs of the register 2 to the information inputs of the decoder 11, a signal appears at one of the two outputs of the decoder 11.

In the command part of the information message received from the slave, recorded on register 2, a write command code (CZ) or End message code from the slave may be contained (CS

If in the command part of the information message from the slave code contains a short-circuit code, a signal appears at the second output of the decoder 11. This signal arrives at the second input of block 8, where through the OR 35 element, the read permission 1 signal (THU 1) is generated at the eighth output of the block 8 and at the same time through the element OR 37 signal Accessing the AMS (17th output of block 8), which plays the role of a clock signal arriving at the synchronous input of block 14.

In register 1, the address of the slave selected for the transmission of information from it, which further performs the function of the attribute, is recorded.

The signal at the second output of the decoder 11 also, acting on the second

In the first cell of each information zone of block 14 the address of the corresponding slave is placed.

In the second cell of each information zone of unit 14 is placed

the input of block 8, through the OR element 38, and also in parallel through the OR element 39 and the delay element 46 generates control signals on the sixth and ninth outputs of block 8; These signals are respectively a signal of the code of the feature from register 1 to the address inputs of block 14 and the code enable signal to register 5 (the mask modification register) and to the corresponding inputs of the indicated registers. Delay element 46 is required for delaying the control signal at the input of register 5 for the time required for operation of block 14 and for the appearance of information on its output data bus.

The signal CHT1 through the OR element 12 also sets the trigger 13 to 1 and the signal defining the read operation appears at the input of block 14

information from block 14.

The logical block is divided into zones, the recording or reading of which is determined by the signs previously recorded in the attribute part of block 14 and

coinciding with the addresses of the WU, which can exchange information with the computer. In the direction I, each such VU as a result of the operation of the proposed device exchanges information with a computer with information blocks, the maximum length of which is determined by the length allocated to this VU zone of block 14.

The information is output by the device on the computer either by filling the zone of block 14 corresponding to the given slave, after which the zone is cleared and filled further by issuing information, or by the CS code received from the slave. Thus, the information message generated by the device has the structure

a mask to be defined, in accordance with which a unit of information is recorded from the slave unit to the first free cell of the corresponding information zone of block 14.

The address of the first free cell of the information zone of block 14 is determined by the position of the only mask bit set in the unit. If the information zone of this VU is empty, then the corresponding mask has the form 0100 ,,. 00 (before modification1

4. The mask arriving at the end of the described operations on register 5 determines the cell of the information zone of block 14, in which in the previous cycle of the device operation with data of the slave unit, information unit j received from this slave was recorded. Thus, to select the next free cell modify the mask by moving the contents of register 5 by one bit to the right. To do this, from the generator 26 of block-8, a shift signal is received on the shift register 56. A single signal appears at the unit second output of register 56, forming the following control signals at the outputs of block 8:

shift register 5 by one bit to the right (mask modification) at the 10th output of block 8, this signal is fed to the input of register 5;

installation of the trigger 13 in this way at the input of the block 14 a control signal is formed, defining the operation of recording information in block 14 (the 16th output of block 8), this signal is fed to the zero input of the trigger 13,

through the element OR 40, the trigger 54 is set to O and, thus, at the 14th and 13th outputs of block 8 and, accordingly, a control code appears at the control inputs of switch 10 defining switching to the information inputs of register 14 5 and 6, and the register of the mask, which in this case is recorded in block 14, uses register 6, which is set to 010, .. 00.

Thus, in place of the old mask in the next cycle of the current operation cycle of the device, the value of the modified mask recorded in register 5, which in this case performs the function of a register from which information is written to block 14, is written

5, In the next clock cycle from generator 26 of block 8 to shift register 56

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five

0

a shift signal is received, and a single signal is generated at the unit third output of this register, whereby the control signals appear at the next outputs of block 8;

through the element OR 41 on the eleventh output of block 8 (Signal to output the code received at the input of register 5)

at the twentieth output of block 8 (signal Exit code at the input of register 6),

through the element OR 38 at the sixth output of block 8 (Signal to enter the code received at the input of register 1)

through the element OR 37 at the seventeenth output of block 8 (signal Appeal to the CAM arriving at the input of block 14),

Under the influence of these control signals and arriving at the address and information inputs of block 14 5 codes, the modified mask is written into the corresponding cell of the corresponding information zone of block 14,

6. In the next cycle, the unit of information received from the control unit and recorded on register 3 is written to the cell of the corresponding zone of block 4. The cell address is determined by the current mask value on register 5.

From the generator 26 of block 8, a shift signal arrives at the shift register 56, and a signal is generated at the first output of this register, resulting in control signals appearing at the following outputs of block 8:

Trigger 54 is set to 1, and at the 14th and 13th outputs of Block 8, a code combination appears, defining the connection of registers 3 and 5, and the register of the mask is performed by register 5J

through the element OR 37 on the seventeenth output of block 8 (signal Accession 50 to the CAM) J

through the element OR 38 on the sixth output of block 8 (signal Output code from register 1.)

. through the element OR 41 on the eleventh output of block 8 (signal to extract code from register 5)

at the fourth output of block 8 (signal Output code, incoming - at input, register 3),

0

35

40

55

Thus, a unit of information received from this WU is recorded in the first free cell of the corresponding information zone of unit 14.

After modifying the mask, the situation is possible in which the unit appears in the (K + 1) th register register 5, i.e. in the previous cycle of operation of this VU with the device, the information zone of this VU was filled, information from it was passed to output register 4, after which the zone was cleared. In this case, the control input of the register 5 is supplied with a control signal from its single output (K + 1) -th bit and the register 5 is set to 0010 ... 00. After that, if in the command part of the current information message from the control unit, the CS code combination is not included, then operations are performed to record a unit of information from the control unit to the first free (in this case, the third) cell of the corresponding information zone of block 14.

If the recording of the next information from the slave does not lead to the complete filling of the corresponding zone, the device ends the cycle of its work with the slave data. The signal from the single first output passes through the chain of the OR element 42, the delay element 47, the OR element 43 and the AND element 30, and the output of the OR element 36 produces a single signal that sets the shift register 56 to 100..OOj and the trigger 44 - To O. Thus, a single signal from trigger 44 arrives at the input of element AND 27, and a single signal is taken from the second input of element 28. The annular shift register 16 of block 7 begins to flow through the element 27 and the shifting signals from the generator 26 of block 8, allowing you to select the next slave ready for the implementation of the exchange operation in direction I.

7. If the recording of the next information from the MU leads to the complete filling of the information zone corresponding to this CU, as evidenced by the unit in the Kth discharge register 5 after modification, then at the end of the cycle of recording the information unit in block 14 the message described

03069

the structure is issued on the output

register 4. This happens as follows.

The sixth input of block 8 receives a single signal from the unit output of the K-th bit of register 5.

Through element 2I-OR 55 and element 48, which is necessary for delaying the signal that initiates reading from block 14 and other signals for the time required for writing to the corresponding information zone of block 14, the last unit of information from the slave unit (it can also be ), at the outputs of block 8, the following signals are generated:

on the seventeenth output of block 8 signal Appeal to

at the seventh output of the block 8 signal 2Q Reading 2 (Ч2), which sets the trigger 13 to 1 through the element OR 12} thus, at the input of the block

14, a signal is generated defining a read operation from unit 14 of this

The 25 output of the block 8 to the input of the register 4 is fed to the control signal of the code enable resolution codeJ

at the sixth output of block 8, a signal. To remove a code from register 1. 30, the action of the described control signals records the generated message to register 4. From the output register 4, this message can then be sent to the information output 66 of the device and transmitted to computer for processing.

The bits of the output data section of block 14, corresponding to the masks of the mask, do not commute with the information inputs of register 40 4. Thus, in register 4, a message of the described structure is generated.

From the output of the element 48 a single signal is fed to the input element

ds 50.the delays necessary for delaying the signals providing zeroing of the corresponding information zone of block 14. These signals are generated at the sixth and eighteenth outputs of block 8. From the eighteenth output of block 8, the signal 14 of the information zone of the block 14 is applied under the influence of the control signal from the sixth output of block 8 of register 1 to the address inputs of block 14. The mask in the second cell of the information zone is set to 010 ... 00.

35

50

55

the output 67 of the device is generated; a signal is generated. The end of the exchange operation with WU is through the OR element 42, the delay element 47, the OR element 43, the AND 30 element, the OR element 36 and the AND 31 element. This signal can be used to initiate the transfer generated on the register 4 messages for further processing in a computer. 9. Consider the situation where, in the command part of the current information message from the slave unit, instead of the short-circuit code, the CS code, i.e. WU - 15 element OR 36 signal, set the information in the directional shift register 56 to 100 ... 00

ten

completely filled, the device generated an informational message and sent it to output register 4,

In this case, the CS code is not recorded in the information zone of block 14 corresponding to this control unit, and the signals of the CS and the signal at the third input of block 8, indicating that the third bit of the register 5 of the modified mask is one, forms the elements AND 33, the element OR 43, the element AND 30 and

SRI I.

In this case, the device repeats the sequence of operations described in paragraphs. 1-8, with the difference that the CS code is pre-recorded in register 3 and is further treated as a unit of information received from the slave. Thus, the following sequence of operations is completed.

Similar to that described after the execution of operations on PP. 1-3, at the fifth output of block 8, a signal is generated enabling decryption and arriving at the control input of the decoder 11.

In accordance with the contents of register 2, a single signal appears at the first output of the decoder 11, which arrives at the first input of block 8 and then through the OR element 57 and the input of register 3. At the same time, a signal is fed to the input of register 2 from the first output of the decoder 11. Thus register 3 is the code of the COP.

The signal from the first input of the block 8 also goes through the element AND 32 to the single input of the trigger 53, setting it to l.

Further, the operations described in paragraphs. 3-8, with the difference that the role of the signal at the second input of block 8 performs a single signal at the output of the flip-flop 53.

An exception is the case when, in an described situation, after modifying the mask, it turns out that its third bit is set to 1. This indicates that the information zone corresponding to this VU is empty, i.e. in the previous cycle of operation of the device with a dan element OR 36 a signal that sets the shift register 56 to 100 ... 00

completely filled, the device generated an informational message and sent it to output register 4,

In this case, the CS code is not recorded in the information zone of block 14 corresponding to this control unit, and the signals of the CS and the signal at the third input of block 8, indicating that the third bit of the register 5 of the modified mask is one, forms the elements AND 33, the element OR 43, the element AND 30 and

0

0

five

and trigger 44 in O. Further, the process of sampling the next VU is possible.

Consider the exchange process in direction II.

Information exchange in direction II is possible between a computer and a control unit, which at the time an exchange request from the computer in direction 5 arrives at input 68 of the device II does not work with the device in direction I. begins exchange in direction II.

The exchange in direction II is as follows.

On the inputs of the decoder 23 block.7 on the group of address inputs 58 of the device comes from the computer address of the required WU.

At the inputs of the transmitter 22 of block 7, the group of information inputs 59 of the device receives information from the computer for the slave.

The exchange request signal is received from the computer at the device input 68 to the unit input of the trigger 24 of block 7 and sets it to 1. This unit goes to the control input of the comparison node 19, allowing this node to check the code combinations coming from the outputs of the element group AND 18 of the block 7 and from the outputs of the decoder 23, on the identity.

A code combination from the inputs of the elements And 18 defines a device selected and exchanging in the direction I. The code combination with. the outputs of the decoder 23 determines the slave required by the computer for exchange in direction II. In case of their coincidence, a zero signal is formed at the output of the comparison node 19 and the exchange in direction II is blocked,

five

0

five

as there is no information permitting the passage through the transmitter 22 to the corresponding WU single signal at the control input of the transmitter 22.

In case of a mismatch between the indicated code combinations, the comparison node 19 generates a single signal at its output. As a result, information is transmitted from the computer to the control unit through the transmitter 22. The signal from the output of the comparison node 19 also arrives at the delay element 21, which, after the time required for the end of the transients in the transmitter 22, generates a signal at its output to all the second inputs ; groups of elements 1-7, the first inputs of which are connected to the outputs of the decoder 23. Thus, at the output of one of the elements 17 of the group and, therefore, at one of the outputs of the group of outputs 65 of the device, a signal is generated that initiates the operation exchange of the corresponding TU.

From the outputs of the transmitter 22, which is a group of informational, outputs 64 of the device, information is sent to the corresponding WU information blocks.

The end of the information message from the computer to the slave is determined by the arrival of the code combination at the inputs of the distributor. The end of the message from the computer. This code combination passes to the outputs of the transmitter 22 of block 7 and is directed to the corresponding WU and simultaneously to the inputs of the decoder 20, which in this generates a single signal at the output, sets the trigger 24 to O, and the single signal from the zero output of this trigger the input input of the comparison node 19, setting O at its output and blocking the further passage of any information through the transmitter 22.

Upon receipt of the next request from the computer for an exchange in direction II, the described operations are repeated.

Claims (3)

1. A device for interfacing a computer with external devices, comprising a control unit, a memory unit, two switches, two registers, so that, in order to expand the area, by providing simultaneous two third-party data exchange between the computer and external devices, a request processing block, a masking node, a decoder, four registers, a trigger, an OR element are entered into it, the first and second groups of information inputs of the request processing block form groups of device inputs for connecting respectively to address groups and information outputs of the computer, the launch input of the query processing unit is the input of the device for connecting to the output of a request to exchange a computer, the information output of the first register is the output of devices for connecting to the information input of a computer, the first output of the control unit is the output of a device for connecting to the recording entry of a computer, the third group of informational inputs of the request processing block forms a group of inputs for connecting to the outputs of readiness of external devices, the first and second groups of information inputs of the first switch form groups of inputs of devices for connecting respectively to the address and info external outputs, the first, second and third groups of information outputs of the request processing block form groups of device outputs for connecting respectively to the address, information inputs and inputs of external devices, the second output of the control unit is connected to the input of the second register, the first information input of which connected to the first output of the first switch, the second and third outputs of which are connected to the information inputs of the third and fourth registers, respectively o, the recording inputs of which are connected to the setup input of the first register and the third output of the control unit, the fourth output which is connected to the read input of the second register, the second information input of which is connected to the information input of the decoder and to the output of the third register, whose read input is connected to the first output of the decoder and to the first input of the logic condition of the control unit, the fifth output of which is connected to the gate input decoder. The second output of which is connected to the second input of the logic condition of the control unit, the sixth output of which is connected to the read input of the fourth register, the output of which is connected to the address input of the block. The memory whose low and high bits of the information output groups are connected respectively to the groups of information inputs. the first and fifth registers, the input of the first register is connected to the first input of the element I OR and the seventh output of the control unit- 1, the eighth output of which is connected to the second input of the element OR, I one of which is connected to a single trigger input, single and zero outputs of which are connected respectively to the read enable and write inputs of the memory unit, whose information input is connected to the information output of the masking node, the first group of information inputs of which is connected to the output group of - |. of the first register, the write, shift, I read and synchronize inputs of which are connected respectively with the ninth, tenth, eleventh and twelfth you I moves of the control block, the thirteenth and fourteenth outputs of which i are connected respectively to the first and second control inputs of the second switch, the first, second group of information inputs and the group of outputs of which are connected respectively to the groups of outputs of the second, sixth registers and the second group of information inputs of the masking node, the third and K-th bits of the group of outputs One of the five registers is connected respectively to the third and fourth inputs of the logic condition of the control unit, the fifth input of the logic condition of which is connected to the request output of the processing unit, the requests whose clock input is connected to the fifth output of the control unit, the sixteenth, seventeenth and eighteenth outputs of which are connected respectively, with the trigger inputs of the trigger, with the synchronous input and the installation input of the memory block, the nineteenth and twentieth codes of the control unit are connected respectively to the installation input and the input of the read of the sixth. register, the (K + 1) th digit of the group of outputs of the nth register is connected with the installation input of the fifth register, the group of outputs of the selection of the query processing unit is connected to the group of control inputs of the first switch. 2, the apparatus of claim 1, wherein the control unit contains a shift register, four triggers, pulse generator, eight AND elements, ten OR elements, seven delay elements, AND-OR element, the first input of the first AND element connected to the first inputs of the second, third AND elements and the first OR element and is the first input of the logical the condition of the block, the first input of the second element OR is connected to the first inputs of the third and fourth elements OR, and is the second input of the logical .. block condition, the second input of the first element AND is connected to the second input of the second element AND, and is 5, the third input of the logical condition of the block, the first input of the AND-OR element is the fourth input of the logical condition of the block, the single input of the first trigger is connected to the input 0 of the first delay element and is the fifth input of the logic condition of the block, the outputs of the fourth AND element and the first OR element are the first and second outputs of the block, the output of the first trigger 0 five 0 connected to the single input of the second trigger, to the second input of the first OR element, and is the third and nineteenth output of the block; the first output of the shift register is connected five with the first inputs of the fifth, sixth, seventh OR elements, with the second and third inputs of the AND-OR element, with the second input of the fourth OR element, with the single input of the third trigger, and is the fourth output of the block, the outputs of the fifth AND element, the fourth OR element are the fifth and sixth outputs of the block, respectively; the output of the second delay element is connected to the input of the third delay element, with the third input of the fourth OR element, With the second input of the fifth OR element and is the seventh output of the block; the output of the third OR element dinene with the third input of the fifth OR element and is the eighth output of the block; the output of the fourth delay element 0 15 is the ninth output of the block, the second output of the shift register is connected to the first input of the eighth element OR and is the tenth and sixteenth outputs of the block, the output of the seventh element OR is the eleventh output of the block, the output of the fifth delay element is connected to the first input of the ninth the OR element, with the second input of the eighth OR element and is the twelfth output of the block, the single and zero outputs of the third trigger are respectively. the thirteenth and fourteenth outputs of the block, the outputs of the sixth element AND the fifth element OR, the sixth delay element are respectively the fifteenth, seventeenth and eighteenth outputs of the block, the third output of the shift register is connected to the fourth inputs of the fourth, fifth elements OR, to the second input of the seventh element OR is the twentieth output of the block, while in the control unit the output of the pulse generator is connected to the first input of the seventh element AND and to the first input of the sixth element AND, the second input of which is connected with zero input of the fourth trigger and with zero output of the second trigger, the unit output of which is connected to the second input of the seventh And element, the output of which is connected to the clock input of the shift register, the fourth output of which is connected to the first input of the fifth element And, the second input of which is connected to the zero output of the fourth trigger, whose single input is connected to the output of the second element And, the output of the first delay element is connected to the zero input — the first trigger, the setup input of the shift register is connected to zero The second input of the second trigger, with the first input of the fourth element AND and the output of the ninth element OR, the second input of which is connected to the output of the eighth element And, the first input of which is connected to the inputs of the fifth delay element and the output of the third element And, the second input of which is connected with the second input of the eighth element And with the output of the tenth element OR, the first input of which is connected to the third input of the third element And and with the output of the first element AND, the second input of the tenth to03069I 6 The OR element is connected to the output of the seventh delay element, whose input is connected to the output of the sixth OR element, the second input of which is connected to the input of the second delay element and to the output of the AND-OR element, the fourth input of which is connected to the single output of the fourth trigger 1Q, and the second inputs the third and second OR elements, with the fifth input of the fourth OR element, the sixth input of which is connected to the output of the third delay element, with the input of the sixth delay element, with the second input of the fourth And element, the output of the second element OR-coagulant connected to the input of the fourth delay element, the output of the eighth element 2Q OR connected to a single input of the third trigger. 3. The device according to claim 1, which is based on the fact that the request processing block contains a shift register, two groups of AND elements, an OR element, two decoders, a comparison node, a transmitter, a trigger, a delay element, and a clock the shift register input is The 30 clock input of the block, the output of the OR element is the output of the block request, the single trigger input is the input of the block start, the group of information inputs of the first decoder, the receiver, the first inputs of the AND elements of the first group form the first, second and third groups of information inputs of the block, respectively. the outputs of the first decryption Q of the rator are connected to the first inputs of the elements of the second group, with the first group of inputs of the comparison node and form the first group of information outputs of the block, the group of information outputs before The sensor is connected to the group of information inputs of the second decoder and forms the second group of information outputs of the block, the outputs of elements AND of the second group form the third group of information outputs of the block, the outputs of elements AND of the first group are connected to the group of inputs of the OR element, form the group of outputs block selection, while in the request processing block the group of outputs of the shift register is connected to the second inputs of the AND elements of the first group, second 50 55 17 1403069 The second inputs of the elements of the second group are connected to the output of the delay element, whose input is connected to the control input of the transmitter and to the output of the reference node, the first and second A swarm of control inputs of which are connected respectively to the single and zero outputs of a trigger, the zero input of which is connected to the output of the second decoder. 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