SU1656544A1 - Device for matching computer with communication channel - Google Patents

Abstract

The invention relates to computing and digital automation and can be used in data transmission systems to adapt a peripheral communication interface with a bi-directional parallel interface. The aim of the invention is to increase speed. The device comprises a transmission control unit, a block of direct memory access, bus data drivers, bus address drivers, transfer register, reception register, two shift registers, trunk request register, status register, port decoder, decoder, pulse generator, control trigger. 4 il.

Description

The invention relates to computing and digital automation and can be used in data transmission systems to adapt a peripheral communication interface with a bi-directional parallel interface.

The aim of the invention is to increase speed.

FIG. 1 shows a block diagram of the device; in fig. 2 - the same, block of direct memory access; in fig. 3 - the same, the transceiver control unit; in fig. 4 is the same, the state register.

The device (Fig. 1) contains bus data drivers 1, bus drivers 2 addresses, block 3 direct memory access, decoder 4 ports, decoder 5, control trigger 6, transfer register 7, reception register 8, shift registers 9, 10 , a trunk request register 11, a transceiver control unit 12, a pulse generator 13, a state register 14, inputs-outputs 15, 16, inputs and outputs 17-26.

Block 3 of the direct memory access (Fig. 2) contains the controller 27 of the direct memory access, bus drivers 28. address register 29, the OR element 30, inputs 31-41 and outputs 42-46 of the controller 27.

Transceiver control unit 3 (FIG. 3) contains codec 27, single vibrator 48, element AND 49. element NOT 50, element And 51, 52, element 53, element AND 54, element AND-OR 55, trigger 56 , element 57, trigger 58, element NOT 59, element AND-OR-NOT 60, element NOT 61, element AND 62, inputs 63-68, outputs 69-76 of encoder-decoder 47, element OR-NOT 77.

The state register 14 (FIG. 4) contains the element NOT 78, the element AND-NO 79, the element AND-OR 80, and the triggers 81-83.

Chip type 580 BT57 can be used as the controller 27 for direct memory access.

Chip type 588 VGZ can be used as a coder-decoder 47.

This device is intended to adapt the serial peripheral O (I

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interface with a bidirectional parallel interface, performing serial-parallel and parallel-serial conversion of data transmitted between these interfaces. Moreover, the data in the serial interface can follow a continuous stream, the length of which is limited by the capacity of the fourteen-bit cycle register of the controller of direct access to the memory of block 3. The data and addresses of the parallel interface are fed into and out of the device via bi-directional bus generators 1 and bi-directional bus generators 2 addresses. The output serial data is transmitted from the output 25 of block 21, and is received at the input 26 of block 12. Transmission and reception of serial data is carried out at a frequency of 1 MHz by bipolar phase-shifted signals

The data exchange between the parallel and serial interfaces is carried out by transmission and reception bursts. Data exchange in the serial interface is carried out by sending transmissions towards the periphery with the necessary reception of response messages.

The device contains a programmable control trigger 6, a transfer register 2 and in block 3 a controller 27 in which there are two channels, each of which has a 16-bit register of the initial memory address and a 16-bit register of cycles.

After the power is turned on, the device is given a zero signal, which resets the triggers, registers, and blocks of the device.

The zero signal path in the device is not shown.

The exchange is initiated by a control system, which includes the device that it programs, after which the device issues data from the memory to the serial interface and writes to the memory of the response messages of the serial interface.

When programming a device, the last 7 transfer register is programmed, since after recording information into it, the device automatically switches to the interaction with the serial interface.

The device programming algorithm will be considered on the example of recording information in the cycle register of the first channel of the controller 27. At the time the recording signal is sent to the port at the device output 17 on

Address buses 15 and data buses 16 present information.

The recording signal to the port from input 17 is fed to the control input of bus drivers 1, 2, switching them to receiving information from buses 15, 16. At the same time, the recording signal to the port enters the sync current of block 3, where it passes through the OR 30 element third control inputs

0 state bus formers 1, 2, transfer them to the working state.

The higher bits of the address are sent to the decoder of the 4 port, at the output of which a single potential appears, if the coding of the higher bits of the address corresponds to the device code. A single signal at the output of the port 4 decoder allows the decoder 5 to decrypt the low-order bits of the address. Therefore, at the output of the decoder 5, which is connected to block 3, a chip select signal appears, which informs the controller 27 that it is being accessed, and switches the bus drivers 28 to the translation mode

5 information (a signal to write to the port and address bits AO-AZ) to the controller 27. At the same time, the input 36 of the data from the controller 27 receives information from the bus driver 1 of the data. The controller 27, having decoded the address code, records information from the input 36 into the low byte of the cycle register of the first channel. To write the high byte, the programming device (for example, a microprocessor) must or5 reorder this register by changing the information at the input 36 of the data,

In controller 27, for each 16-bit register, there is a trigger that

0 after writing the information to the low byte is set to G and when re-accessing the register sends the data to the high byte.

Lower 14 cycle register bits

5 speaks about the number of memory access cycles.

One cycle is a one-time writing or reading of the contents of a single memory cell.

0 The two most significant bits are used to indicate the direction of information (write or read) when interacting with an external memory.

The starting address register is for

5 messages with which initial memory cell will be an interaction (write or read).

The first channel of the controller 27 serves to organize the reading of information from the memory. Read device information translates to a serial interface. Information from the serial interface using the second channel of the controller 27 is recorded in a memory.

During the first cycle of accessing the memory, the controller generates the address of the memory location equal to the initial address, and in each subsequent cycle the address is incremented by one until the number of memory access cycles becomes equal to the specified one. In this case, the controller 27 generates a signal KS.

A control trigger 6 is programmed when an array of information is transmitted to the serial interface.

If one word is transmitted, the control b trigger will remain in its original state.

Consider the mode of issuing a single word to the serial interface and receiving a response array of information from it.

In this case, the programming device writes zeros to the starting address register and the cycle register of the first channel, and the number of write cycles to the memory register in the register of the starting address of the second channel. The control trigger 6 in this case remains in the initial state, and the information in the transmission register 7 is written to the serial interface.

The data will be recorded in the transfer register 7 if there is an enabling signal at the output of the decoder 5 connected to the transfer register 7 and block 12. And if there is a recording signal to the port at input 17.

If these signals are present, the data from the bus drivers T will be recorded in the transfer register 7 and simultaneously the trigger 56 of block 12 will be set to state G, since the signals arriving at the first synchronous input and the first input of the logic condition of block 12 will coincide on the AND-OR element 55 After the flip-flop 56 is set to state 1, the first pulse on the third synchronous input of block 12 generates a signal at the output of the element 57, which is fed to the synchronous input of register 9, by rewriting the contents of transfer register 7 to shift register 9, and The C input of the trigger 58 sets it to state 1. The zero signal from the zero output of the trigger 58, the passage through the element NOT 59, AND-OR-NOT 60, sets the trigger 56 to the initial state, and the single signal from the single output trigger 58 , acting on the input 68 of the encoder-decoder 47, translates it into transmission mode. The input 66 of receiving the serial data of the encoder-decoder 47 is connected to the information output of the shift register 9.

After installing signal 1 at input 68 of encoder-decoder 47, it switches to transmission mode and independently forms a marker, which is output via outputs 73 (bipolar zero) and 74 (bipolar unit) at a frequency of 1 MHz. After issuing a marker on

0, the output 76 of the encoder-decoder 47, a signal 1 is generated, which is requested data for transmission. This signal, arriving at element 52, permits the passage of 1 MHz clock signals from output 75 to output

5 shift information register 9 shift.

When the contents of the shift register 9 will be transmitted to the serial interface via the outputs 73, 74 of the encoder-decoder 47, the signal 1 from the output 76 is removed, the shift

0 information in register 9 is terminated, and codec 47 itself generates and outputs a parity check bit

This completes the single-word cycle. At the time of occurrence of zero

5, the signal at output 76 clears trigger 58 and a zero potential is established at input 68, which prohibits subsequent cycles of outputting information from the device. Trigger 58 resets the path - exit

0 76, the element is NOT 53, the element is AND 54, the element is OR-NOT 77 is the zero input of the trigger 58. Resetting the trigger 58 by the signal from the output 76 is allowed, because the second input of the element And 54 has a signal 1, i enter

5 from the element HE 61, at the input of which the potential O is coming from the single output of the control trigger 6. In the single word output to the serial interface, control trigger 6 is in zero

0 state. Due to this, the impulse that sets the trigger 58 to one state does not pass through the element 62 and does not set the first register register 11 to 1 and the block 3 does not organize the request

5 memories.

In response to the word transmitted to the serial interface, data from it are received, which, through inputs 26, arrive at inputs 63 of bipolar zero and 64 bipolar

0 units of the coder-decoder 47 block 12.

The received data is decoded by the encoder-decoder 47 and, in the presence of a reliable marker and two subsequent bits of the data, are issued

5 code through the output 72 to the information input of the shift register 10, to the input of the shift of which information the shift pulses are received from the output of the element 51 of block 12. The synchronization pulses of the received information from the output 71 of the encoder-decoder

47 passes to the output of the AND 51 element when a single signal is present at the output 69 (data sending) of the encoder-decoder 47. The single signal at the output 69 is held for the duration of the output of the serial data from the output 72. After receiving the data, the encoder-decoder 47 analyzes the received This compares the information with the check bit and, at the falling edge of the data sending signal (output 69), generates a single signal at output 70 if the received information is compared with the check bit, and otherwise, output zero at 70. On the falling edge of the data sending signal (output 69), a one-shot 48 is triggered, at the unit output of which a short signal is generated that overwrites the information from shift register 10 into reception register 8 and sets 1 second register of request 11. The signal from the output of the one-shot 48 through the element I 49 sets the first digit of the first register register to 14, if the received word is distorted. In this case, at the output 70, a zero potential, which at the output of the element NOT 50 forms a single potential that permits the passage of the signal from the one-shot 48 to the state register 14.

A single signal from the second bit of the register 11 of the request is fed to the input 38 of the controller 27 of the block 3. Upon receiving a request to access the memory (ZPD2), the controller 27 exposes at the output 20 a request to capture the main from output 45. If the parallel interface is free, then on input 21, the enable signal for interaction with the highway arrives at input 39 of controller 27, and controller 27 organizes a cycle for writing the contents of register 8 to a memory. For this, it generates a single signal at the output 42 (PA), which, passing through the element OR 30, goes to the bus driver 1.2 and switches them to the working state. And since there is no recording signal to the port at input 17, the bus drivers 1,2 and 28 are in the mode of information transmission from the device to the parallel interface and from the controller 27 to the address output of block 3, respectively. After the PA signal is issued, the controller 27 through the outputs 34, 33 outputs the code of the low byte of the address, and through output 36 the code of the high byte of the address, which goes to the information inputs of the address register 29 and is written to it from the output 35 of the controller 27. After recording the high bytes of the address in the register 29 we have on tires 16 data the contents of register 8 of reception, on buses of address 15 - the code of the address of the first

memory cells from the address register 29 and the outputs 33, 34 of the controller 27, Then the controller 27 at the output 44 (RFP) forms the leading edge of the memory recording signal,

which at exit 28 enters the computer's RAM. RAM, receiving a signal from output 18, writes data from bus 16 to a memory cell, the code of which is specified on address buses 15, and on input 22 issues a confirmation signal

execution of the command, on the leading edge of which the request register 11 is reset, and on the falling edge, the controller 27 forms the falling edge of the write-to-memory signal. There is a memory circulation cycle.

is running out.

Simultaneously with accessing the memory, the device continues receiving the next word from the serial interface to the shift register 10 under control of the block

12. After receiving the next word in register 10, a new cycle of memory access is organized according to the algorithm described above. This process is repeated until the last word is reached. When

the last word will be recorded in the memory and at input 22 a signal will arrive confirming the execution of the command (write to the memory), the controller 27 at output 46 (CS) generates a signal for the end of the interaction, which

sets state 1 to the second state register 14. Then a signal appears on the interrupt input that tells the parallel interface to terminate the interaction with the serial interface.

To organize the next interaction with the serial interface, the device must be reprogrammed and reset.

Consider the mode of issuing an array of information to a serial interface and retrieving one response word from it. In this case, a trigger is programmed

6, the starting address register, the cycle register of the first channel of the controller 27, the register of the starting address of the second channel, and the zeros in the cycle register of the second channel are entered. Last programmed

transfer register 7, after which the device performs the specified exchange mode. The copying of information from the transfer register 7 to the shift register 9 is carried out in the same manner as described above. The signal from the output

element And 57 sets not only the trigger 58, but also the first bit of register 11. The unit state of the trigger 58 allows the codec 47 to output a word from shift register 9 to the serial interface.

In the process of issuing a word to the serial interface, a single signal from the first bit of register 11, inputted to input 37 of controller 27, causes the controller to issue a request signal for the backup bus from output 45. When receiving a capture confirmation signal from input 21, controller 27 organizes a memory access cycle For example, the read-access memory cycle coincides with the write-write cycle described above and differs from it only by the command issued. Instead of the write-to-memory signal (FOD), a memory read signal is output from output 43 (PTP) of the controller 27. Simultaneously with the PTP signal, the controller 27 outputs an input / output write signal from output 32 (EPV / V), which is fed to the synchronous input transfer register 7 and writes the contents of data buses 16 through driver 1 to transfer register 7. After the output of the shift register 9 is output, the back edge of the signal is formed at the output 76 of the encoder-decoder 47, in which the trigger 56 of the block 12 is set to one in the array transfer mode via the AND-OR element 55. As a result, the cycle of outputting the contents of the transfer register 7 through shift register 9 in the serial interface is repeated. This cycle will be repeated until the last word of the array is written to transfer register 7. Then the controller 27 will generate the signal End of the interaction at the output 46, which is fed to the input of the element OR-NOT 77 of the block 12. Resets the trigger 58, thereby prohibiting the subsequent cycle. The process of issuing the last word of the array from the transfer register 7 to the serial interface is completed when the trigger 58 is in the initial state. At the same time, the signal from the output 46 of the controller 27 enters the state register 14 at the input of the element EH 79 and sets the trigger 81 to the state G.

After the last word is output to the serial interface, a response word will arrive from it after a certain time interval, which is received by control unit 12 in shift register 10, rewritten into receive register 8, the contents of which are sent to memory by block 3. Since the cycle register of the second channel of the controller 27 contains zeros, the controller 27 at the output 46 will generate a signal for the end of the interaction, which, arriving at the input of the AND-OR 80 element of the state register 14, sets to state 1 a trigger 82, telling the programming device about the end of interaction with the serial interface.

If in the process of receiving information from the serial interface, the received word is not compared with the check bit, the output 70 of the encoder-decoder 47 will have a zero potential that allows the signal from the one-vibrator 48 of the control unit 12 to set the trigger 83 of the register 14 to one state neither

0 A single signal from trigger 83 to

output 23 of the interrupt enters a parallel interface warning the programming device about the distortion of the received word.

Claims (2)

1. A device for interfacing a communication channel with a computer, comprising bus data drivers, a transmission register, two shift registers, a reception register, a transceiver control unit, a decoder, a status register, the groups of information inputs and outputs of the transceiver control unit form groups of inputs and the outputs of the device for connecting to the communication channel, the first and second outputs of the status register are the outputs of the device for connecting respectively to the first and second inputs of the computer interrupts, the inputs-outputs of the bus form vate0 leu data form a group of input-output device for connection to a group of information inputs of the computer outputs, characterized in that in order to improve performance, introduced into the device 5 block direct memory access, port decoder, bus address drivers, control trigger, pulse generator, trunk request register, the first synchronous input of the transmission register is connected 0 with the first synchronization input of the transceiver control glare, with the synchronization input of the control trigger, with the first control inputs of the bus data drivers and the address information drivers, with the synchronization of the direct memory access unit and the input of the device for connection to the computer synchronous input, inputs-outputs bus address drivers form a device I / O group to connect to a group of computer I / O addresses, write, read, request to capture the trunk and input to confirm the capture of the trunk of the drive unit. direct access to the memory are vyhoda5 inputs E and apparatus for connecting respectively to the inputs of the recording, read-line capture request and acknowledgment output line capturing computer, ready input unit direct access memory is connected to the adjusting input of register request line and is the input of the device to connect to the output of the confirmation of the execution of a computer command, while the information outputs of the bus data drivers are connected to the information inputs of the direct memory access unit, the control trigger, the transfer register, the information output of the transfer register is connected to the information the input of the first shift register, the information output, the synchronous input and the shift input of which are connected respectively to the information input, to the first and second outputs of the receiver control unit The first input of the logical condition is connected to the recording input of the transfer register and the first output of the decoder, the second output of which is connected to the enable input of the control trigger, the single output of which is connected to the first installation input of the state register and the second input of the logical condition transceiver control unit, the second synchronization input of which is connected to the first synchronization output of the pulse generator, the second synchronization output of which is connected to the clock input of the direct memory access unit and to the third by the input of the transceiver control unit, the third input of the logic condition of which is connected to the output of the interaction of the direct memory access unit and the second setup input of the status register, the third installation input of which is connected to the third output of the transceiving control unit, the fourth output of which connected to the synchronous input register of the receive register and to the first information input of the request trunk register, the second information input of which is connected to the fifth output of the transceiver control unit, The second and seventh outputs of which are connected respectively to the shift input and the information input of the second shift register, whose information output is connected to the information input of the reception register, whose information outputs are connected to the information inputs of the bus data drivers, the second control inputs of which are connected to the second control the inputs of the bus address formers and I mean, the output of the direct memory access block whose address outputs are connected to the information inputs of the address bus drivers, the first information outputs of which are connected to the information inputs of the port decoder, the output of which is connected to the enabling input of the decoder, the third output of which is connected to the enabling input of the direct memory access, the address inputs of which are connected to the information inputs of the decoder and to the second information outputs of the bus address drivers, strobe the output, the first and second inputs of the request of the direct memory access unit main are connected with the second synchronous input register, respectively, with the first and second the outputs of the query register highway. 2. The device according to claim 1, characterized in that the transceiver control unit comprises a codec, a one-oscillator, two triggers, six AND elements, four NOT elements, an OR-NOT element, an AND-OR element. the AND-OR-NOT element, where the group of information inputs and outputs of the encoder-decoder form, respectively, the groups of information inputs and outputs of the block, the information inputs and output of the encoder-decoder are respectively the information inputs and outputs of the block, the first input of the AND-OR element and the first sync input the coder-decoder are, respectively, the first and second block syncs, the second sync input of the encoder decoder is connected to the first input of the first AND element and is the third synchronized input of the block, the second input of the AND-OR element is the first input of the logical condition of the block, the third input of the element AND - OR is connected to the input of the first element NOT, with the first input of the second element AND is the second input of the logical condition of the block, the first input of the element OR NOT is the third input of the logical condition of the block, the output of the first element And is connected to the sync input of the first trigger, with the second input of the second element And is the first output of the block, the outputs of the third and fourth elements And are respectively the second and third outputs of the block, the output of the one-shot is connected to the first The fourth input of the fourth element AND is the fourth input of the block, the output of the second element AND is connected to the first input of the element AND-OR-NOT and is the fifth output of the block, the output of the fifth element AND is the sixth output of the block, while in the control unit transceiver second input of the fourth element And is connected to the output of the second element NOT, the input of which is connected to the output of the control sign of the encoder-decoder, the output of the data attribute of which is connected to the start input of the one-vibrator and the first input of the fifth element And, the second input of which dinen with the output synchronization reception of the encoder-decoder, the synchronization output of the transmission of which is connected to the first input of the third element And, the second input of which is connected to the output of the coder-decoder request, to the fourth input of the AND-OR element and to the input of the third element NOT, the output of which is connected to the first input of the sixth AND element, the output of which is connected to the second input of the OR-NOT element, whose output is connected to zero input of the first trigger, the zero output of which is connected to the input of the fourth element is NOT. the output of which is connected to the second input of the AND-OR-NOT element, the output of which is connected to the zero input The second trigger, the sync input and the unit output of which are connected respectively to the output of the AND-OR element and to the second input of the first element AND, the output of the first element is NOT connected to the third input of the AND-OR element and the second input of the sixth element AND, the single output of the first trigger connected to the start input of the encoder-decoder, the first and second information inputs of the first and second triggers are connected respectively to the buses of the unit and zero potentials of the device. (pusi fig