SU1672459A1 - Computer-to-external storage interface unit - Google Patents

Abstract

The invention relates to computing and can be used to communicate peripheral devices with a computer. The purpose of the invention is to increase the speed of information exchange while reducing the channel acquisition time. The goal is achieved in that a device containing a block of registers, a block of channel drivers, an encoder of states and a trigger for a direct access request, is entered with an AND - OR - NOT element. 7 il.

Description

The invention relates to computing and can be used in computer complexes for connecting external drives to computers, for example, on magnetic tape.

The aim of the invention is to increase the speed of information exchange.

Figure 1 shows the block diagram of the device; figure 2 - functional diagram of the block of registers; on - functional address decoder circuit; Fig 4 is a functional block diagram of channel drivers; Fig 5- / - timing charts of the device.

The diagram (FIG. L) shows the external drive control device 1 connected to the register block 2, the address decoder 3 and the direct access trigger trigger 4, the channel driver unit 5, the AND-OR-HE element 6, the encoder) states and the computer 8 .

Unit 2 of registers is designed to receive and transmit information from a computer

with the General bus channel and contains (Fig. 2) the register 9 of the transmitted ones, the register 10 of the transmitted address, the register 11 of the transfer state, in which the lower two bits are the high bits of the address, the high bits are the exchange type bits (input, output, output byte), the register 12 of the received data (with three states at the output), the register 13 of the received address, the register 14 of the receive state, E which the lower two bits are the high bits of the address, the high bits are exchange type bits

The address decoder 3 (FIG. 3) is intended for determining the access of the computer to the device registers and consists of a latch type register made on AND-OR-NOT 15 and 16 elements, comparators 1 / and 18 on AND-OR-NOT elements (AND elements -OR-NOT can be implemented on the integrated circuit of the programmable logic matrix KM1556HL8) and the element AND-NOT 19,

100

WITH

ABOUT

XJ N5 N SL O

Block 5 of channel formers (FIG. 4) serves to form the reception and transmission to the computer of signals controlling the exchange of information, and consists of AND elements 20-22, NOT elements (inverters) 23-25, delay elements 26-29, channel 30-33 transceivers, triggers 34 and 35, and an AND-OR-NOT 36 element

The encoder / can be executed on the integrated circuit of the programmable logic matrix KR556RT2S

Fig. 1-4 also shows lines (buses) 3 / -63 of interblock and external connections, with lines 37-43 forming a group of outputs, and line 44 — the output of the encoder of 1 states, lines 50, 51, 60 and 62 forming a group device inputs for connecting to the control group of external storage device outputs

On lines 3 / -63, signals of the following functional purpose are formed: line 3 / - channel is busy (direct signal), line 38 - synchronization of the passive device, line 39 - confirmation of the choice, line 40 - resolution of data transmission to the channel, line 41 - synchronization of the active device, line 42 - service request for software exchange, line 43 - service request in direct access and interruption modes, line 44 - device status is occupied by the channel, bus 45 is bi-directional data bus, bus 46 is the address bus and data channel computer line 47 - control write to the register 12 received data, line 48 - write control to register 9 transmitted data, line 49 "O - write control to address register 10, line 49с1 - write control to address register 11 and exchange direction, line 49 l 2 - resolution the third state of the receiving data register 12, line 50 - setting the requirement of direct memory access, line 51 - managing the direct memory access mode, line 52 - receiving address outputs, line 53 - exchange receiver output, line 54 - exchange receiver output, 55-kan line al is occupied (inverse signal), line 56 - addresses of the device registers, line 5 / "0 - output of the matches of the addresses of the comparator registers 1 /, line 5 /" 1 - request for software

16/2459 exchange, 58o0 line - delayed at0

five

0

five

0

five

0

five

0

five

synchronized signal of the passive device, line 58 "1 - received signal of synchronization of the active device, line 5802 - delayed received signal The channel is busy, line 58 s 3 - sync signal of the channel provision, bus 59 - bus control signals of the computer channel, line 60 - signal software exchange control, line 61 — signal for direct memory access request, line 62 — interrupt request signal, line 63 — passive device synchronization signal received “

The device works as follows.

In the program exchange mode, the device status register is most often read from the Control device 1 after processing the access to this register or after completing the service of direct memory access, or, if the device is not occupied by outputting information in the direct access mode, it occurred a change in the state of this register, writes its contents to the register 9 of the transmitted data of block 2, at the same time the address of the recorded register is recorded in the register of the decoder 3. In this case, when reading the state register computer, va decoder 3 compares the contents of the register and the address that is accessed computer, outputs to the encoder / coincidence signal through line 57.Oo decoder 3 outputs a request to the encoder 7 via line sharing software 57.1 handling device registers, device address registers are set to. lines x 56.3 and 56.4.

Information exchange in the direct access mode is prepared in advance. In the registers of block 2, device 1 records the address, exchange direction and data, if there is information output, then a signal is set from output 50 of device 1, which sets trigger 4 "Direct access is completed as soon as the computer releases Channel "At the end of the direct access cycle, if there was an information output, a service request is generated for the next cycle" If there was an input, it is stored in register 12 of block 2, and a service request is also called, but a checking cycle, according Within a 10

the rum occurs on the computer, outputs the encoder / a coincidence signal via line 5, O, therefore, the software exchange of the control device 1 is not required. The encoder / states outputs, via block 5, the synchronization signal of the passive device, i.e. the channel is occupied at the minimum:, two times smaller, the period of time,

The comparator 18 generates a signal on the encoder / status on line 5/1 of the program exchange request (calls to the device registers), the addresses of the device registers are assigned at the inputs 56.3 and 5604

Element And 20 of block 5 (Fig „4) delays the start of transmission of the synchronization signal of the passive device (line 38) to the computer line 8, elements 21 and 22 remove the channel request signals in the direct memory access and interrupt modes when installed by the encoder / Signal Channel is busy (line 3 /) Elements 21 and 22, inverters 24 and 25, and triggers 34 and 35 are used to form the request signals and provide the channel in direct memory access and program interruption modes. The initial state of the outputs of the inverters 24 and 25 is the logic level O, the outputs of the flip-flops 34 and 35 are 1. If the device is not requested, it is stitching the channel, then

21 or 22 and at the cleaning input of the corresponding trigger 34 or 35, which has been triggered by the installation of the trigger 4,

Element 6 generates a write pulse to register 12 (FIG. 02) when recording a computer from a channel to a device register and entering information in direct memory access mode. During software exchange and information exchange in direct access mode, the transmitted data registers 9 and received data 12. In order to avoid the loss of information arising in this case, signals 1 are sent to device 1 along lines 38, 44 and 61 (Fig. 1). reflecting the state of exchange.

For the exchange of information in the mode of direct access to memory, registers 10 and 11 of block 2 (Fig. -2), device 1 records the address and direction of exchange, the data in register 9 are recorded if there is information output. After the end of the direct access cycle, if there was an information output, a request for service for the next cycle of direct memory access is triggered. If there was an information output, it is stored in the receiving register 12 of the block

20

and

a request is made to service the current cycle of direct access to the memory of

If direct memory access was initiated and data was recorded in register 9, the computer channel

while the computer i requested to read the device’s register, then, when servicing the register, device 1 rewrites the requested information to register 9, waits for the passive device’s synchronization signal to be removed from line 38, and restores the previously recorded information, On the other hand, before initializing Access device 1 checks the signal on line 44 to determine if the channel is busy servicing the device from

When a computer requests a device register to read, data is written from device 1 register to register 9 (fig 2) of block 2 by a signal on the 48 ° line. At the same time, the register address of device 1 is recorded at input 56 in the decoder register 3 (elements 15 and 16, 3) 0 Further, when reading a computer 8 of the register of the device, comparator 1 / compares the contents of the register and the address to which

logical level 1, when the signal from the computer 8 signal

40 of the channel provision at the output of the corresponding inverter 24 or 25 is the logic level 1, the state of the flip-flops does not change, the signal of the channel is not passed through the device. If there was no channel request, the output of element 21 or 22 and the cleaning input of the corresponding trigger 34 or 35 is the logic level O, and since the installation is the same as the input, then the output

of these triggers, there is a logic level 1, when a channel-assignment signal at the output of the corresponding inverter arrives from the computer channel 8

55 24 or 25 - the logical level 1, so that the level O is present only at the trigger cleaning input Therefore, at its output O, which corresponds to the transmitted signal

ten

20

thirty

logical level 1, when the signal from the computer 8 signal

the channel is provided at the output of the corresponding inverter 24 or 25 — logical level 1, the state of the flip-flops does not change, the signal of the channel is not passed through the device. If there was no channel request, the output of element 21 or 22 and the cleaning input of the corresponding trigger 34 or 35 is the logic level O, and since the installation input is the same, then the output

of these triggers, there is a logic level 1, when a channel-assignment signal at the output of the corresponding inverter arrives from the computer channel 8

24 or 25 - the logical level is 1, so the O level is present only at the trigger cleaning input. Consequently, O is at its output, which corresponds to the transmitted signal.

channel allocation element, AND-OR-NO 36 generates a channel-provisioning signal in forward access and interruption modes delayed on the leading edge to control the encoder 1,

The encoder / states generates the signal sequences of the channel of the common bus (GO IPC software BT 34-80) ",

The contents of all software-accessible device registers are stored in the registers of control device 1. To read in the mode of program exchange with the computer 8, it is necessary to transfer the contents of one of the registers of device 1 to register 9 (FIG. 2), to write to these registers it is necessary to transfer the contents of register 12 to the corresponding register of device 1 (specified for 52). the data transmitted to the computer in register 9 simultaneously with the same signal records the register address of device 1 into triggers 15 and 16 of decoder 3 (FGSZ), so that when reading the computer registers of the device, if these addresses are the same, the device 1 does not require service th exchange, data from the device 1 registers in the register 9, the output signal of the comparator 1 / is supplied to the encoder / 5 blocks the generation signal on line 42 and allows the immediate issuance of a signal line 38 "

The timing diagram (.fig., 5) displays the program exchange processes with the 8C computer. When accessing the device, the computer 8 exposes its address on the 46 channels of the channel. The decoder 3 decodes it and issues a 5/1 signal to the block 5 (Fig. 5) Next, the computer sends to the bus 46 the synchronization signal of the active device, which through block 5 is fed to the input of the 5811 encoder / if it is written to the device register or read register that is not currently stored in register 12 of block 2 (the beginning of the timing diagram on FIGS5), the encoder / issues a service request for the program Nogo exchange with output 42 in the device 1, the latter terminates the current firmware reads the contents of the register 9 unit 2 and outputs the signal through line 60. After receiving the last encoder / boost signal line 38 in synchronization passive device,

0

five

five

0 5

0

0

five

which, via block 5, enters the computer channel, it removes the signal in line 58.1, the exchange process is completed. If a register is being read that is currently stored in register 12 of block 2 (the end of the time diagram in Figure 5), the encoder immediately issues signal to line 38, and signal from line 42 is not generated by t

The timing diagram (FIGS. 6) displays the exchange with the computer 8 in the direct memory access mode, the process is initiated by a signal in line 50 from the device 1, through which the trigger 4 is installed. The trigger output 61 through the element 21 of block 5 (FIG. 4) and The channel transceiver 31 generates a 5 channel request signal of the direct access to the computer 8 on line 59 and, upon completion of the current exchange process with the memory, outputs to the line 59.10 a channel access signal in the direct access mode, the latter with a time delay forms the logic level O at output 58 about 3 elements 36. P The signal in line 58.3 encoder / sets in line 39 a selection confirmation signal, which removes the channel signal in line 59.5 and sets the signal in line 59.4. The computer 8 responds to the signal in line 59С10, logical level 1 appears at output 58.3, which results to install the encoder in line 3 / signal The channel is busy, and then the synchronization signal of the active device in line 41. The computer 8 responds with the synchronization signal of the passive device (line 63), which takes the signals in lines 3 / and 41 and issues a service request pulse in direct mode memory access resetting trigger 4

The timing diagram (FIG. /) Displays the exchange with the computer 8 in the interrupt mode. The process is initiated by an interrupt request signal (line 62) from device 1 through the element 22 of block 5 (FIG. 4) and the channel transceiver 31, a channel signal for interrupting a request is generated on line 59.6. Upon completion of the current command, the computer 8 gives the line interrupt providing signal 59d1) t The latter, with a time delay, forms the logic level O at output 58.3 of element 36. At a signal in the line

The 5813 encoder / sets the signal to confirm the selection of line 39, which removes the channel signal on line 59.6 and sets the signal on line 59.4. The computer 8 in response removes the signal in

line 59'11, output 58 3 makes it appear that the logic level is 1

The signal for the request for the service in the interrupt mode (lines 3 / and 43) is set to the encoder / signal channel. the device 1 in response to the request produces data (address of the interrupt vector), a pulse in line 48, writing them to the transmitting data register 9 of block 2, and a control signal on line 60 "The latter removes the signal in line 39, the encoder / sets the signal in line 40 which, through block 5 generates a channel interrupt signal (line 59) with computer 8, responds with a synchronization signal of the passive device (line 63), to which the encoder / issues a second service request pulse in interrupt mode (line 43), device 1 in response to the request takes the signal in line and 62, the encoder / removes signals in lines 40 and 59.6, and the computer - a signal in line 63,

Claims (1)

Invention Formula A device for interfacing a PZM with an external storage unit containing a register block and a block of channel drivers, the information input-output groups of which are the corresponding input-output groups of the device for connecting to the address-information and control computer buses, the encoder of states, the first group of inputs the states and the first group of outputs of which are connected respectively to the group of outputs and to the first group of information inputs of the channel driver unit, the address decoder, the first group of information whose inputs are connected to the first 0 blunt, output and reset input connected to the corresponding input and output of the second group of state inputs and group of outputs of the state encoder; the installation input of the direct access demand trigger, the second group of information inputs of the channel driver unit and the second group of state inputs of the state encoder form a group of device inputs for connecting to the group of outputs for controlling the exchange mode, permitting data output of the registrator unit to the corresponding output of the group of outputs of the state encoder o, the output of which is input by the output of the device for connection to the busy input of the external storage device, 0 is characterized in that, in order to increase the exchange rate, an AND-OR-W- element is inserted into the device, the output of the direct access demand trigger is connected to the corresponding input of the second group, i the information inputs of the channel driver unit, the first and second outputs of the connected correspondingly with the permission input of issuing the address and the state of the register block and the first RCS of the I-SHSh-NE element, the second input and the output of which are connected respectively to the corresponding output of the output group of the state coder and 5 to the input of the permission to receive information of the register block, the third input of the I-SHSh-NOT element is connected to the corresponding output of the output group of the state encoder and the synchronization input 0 receiving the address and status of the register block, the fourth input of the I-SHSh-NE element - with the corresponding output of the group of outputs of the register block, the first group of outputs of which is 5 groups of device outputs for connection to the group of address inputs of an external storage unit, the first output of the channel driver unit and the second group of outputs of the relistroy unit the group of outputs of the register register, the corpse-50 is connected to the third group of inputs a data input-output pa, a group of synchronization inputs and the second group of outputs of which are the corresponding groups of input-outputs, inputs and outputs of a device for a sub; data bus switches, a group of synchronization outputs and a group of inputs of the external storage exchange direction, and a trigger for the requirement of a direct status for the encoder, the output group of which is a device output group for connecting to the request storage inputs of the external storage device, a fourth group of inputs for the encoder state the states are connected to the output group of the address decoder, the second group of information inputs and the synchronization input of the address decoder are the corresponding groups of device inputs for connection to a group of outputs and address outputs external sync group accumulator, yield Direct Access Trigger Trigger is connected to the device's output group for connecting an external storage device to the request input ate 1/1 vr CN . VC Pi / r. four FIG R R FIG. 6