SU1508218A1 - User to communication channel interface - Google Patents

Abstract

The invention relates to computing and can be used to interface a remote source of digital discrete information with a computer. The aim of the invention is to increase the reliability of the transmitted information due to hardware information partitioning into separate blocks with its control code. The device contains a synchronization unit, a mode setting unit, a transceiver, a recording node, a switch, a code counter, a buffer register, an input trigger, a recording trigger, an amplifier, two AND elements, two NAND elements and two delay elements. 2 Il.

Description

i

The invention relates to computing and can be used to interface a remote source of digital discrete information with a computer.

The purpose of the invention is to increase the reliability of the transmitted information due to hardware information partitioning into separate blocks with its control code about

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of the task mode,

The device contains (FIG. 1) synchronization unit 1, mode setting unit 2, transceiver 3, recording node 4, switch 5, AND 6 element. code counter 7, buffer register 8, input trigger 9, delay element 10, write trigger 11, element 12: delays, AND-NOT elements 13 and 14,

element 15, amplifier 16, information input input 17, strobe input 18 and output 19 into the communication channel

The mode setting unit 2 forms (figo 2) a one-shot 20, a trigger 21, an AND element 22, a counter 23, a decoder 24, and a code register 25.

The device works in the following way.

When the power is turned on, unit 2 outputs to the switch 5 and node 4 of the recording a series of information and control signals and simultaneously supplies the input to the operating mode of the transceiver 3 with a signal that sets the last programming mode. Switch 5 sequentially transports 3 words of the mode format and command to the information input of the transceiver 3, and node 4 of the record gives the input

WITH

t

ABOUT)

Yu

, 15

recording transceiver 3 write pulse, transceiver 3 exposes a high level signal at the ready output, which enters the input of the AND 14 element, the input of the element I. 6, the counting input of the counter 7, the input information of the trigger 9 input and the input of the element 12 delays. The following sequence of events occurs:

at the output of the NAND 14 element, a low level signal appears, which is fed to the control input of the switch 5;

counter 7 of the code does not change its state, as in the original. the initial moment of blocking in the state O on the setup input, which receives a high level signal from the zero output of the recording trigger 11, which is in the state

the two-digit code determined by the current state of counter 7 of the code goes from the output of the latter directly to the information input, and through the AND 15 -.to element to the control input of the switch 5;

when a strobe pulse arrives from the subscriber at input 18 to the synchronizing input trigger input 9, the latter switches from the state O to the state

on the falling edge of the signal at the zero output of the input trigger 9, the 16-bit parallel information is written from the input 17 to the buffer register 8, from the output of which the information goes to the information input of the switch 5;

In accordance with the value of the code arriving at the relay input of the switch 5 from the output of the element 15, the latter switches four bits of the input information word to the input bus of the transceiver 3 and a two-digit control code that arrives at the information inputs of the switch 5 corresponding to Stenno with the output of the buffer register 8 and the counter 7 code;

the signal passed through the element 10 of the delay from the unit output of the trigger 9 input to the installation input of the trigger 11 entries, the last

switches to state

the signal at the zero output of the f1 write trigger removes the lock from

account 7 code and blocks the trigger 9 input in the state

from the single output of the trigger 11, a high level signal is fed to the input of the NAND element 13, to the second input of which the permit signal has already arrived from the output of the delay element 12;

from the output of the element IS-NOT 13 to the input of the recording node 4, a low-level signal is received, through which a write pulse is generated, which enters the recording input of the transceiver 3, which records information received from the output of switch 5 into the internal memory, and also removes the ready signal its output readiness;

transceiver 3 converts the received parallel information into a serial view and transmits via amplifier 16 to input 19 to a communication channel;

at the end of the transmission, transceiver 3 re-sets the ready signal on the readiness output at CBoeiyT; /

.I-NOT element 14 is working, counter 7 of the code is triggered, from which the changed control code enters the information input, and through element 15 it goes to the control input of switch 5, which switches to the next data bus of the transceiver 3 next four bits. yes input information word and new control code;

after a period of time determined by the delay element 12, and, the IS-NE 13 element is output, from the output of which a recording signal is fed to the input of the recording node 4, which is used by the latter to generate a recording pulse at the output that the transceiver 3 remembers the input information, removes the ready signal from the output and proceeds to; transformation and further processing of the received information.

In a similar pattern, the entire input information word is written to the buffer register 8.

After pedaling the last part of the input information word, transceiver 3 once again exposes the ready signal at its output, the code counter 7 is activated, the code P output, the AND 6 element triggers, the output of which is the signal of post 515

goes to the setup input of the recording trigger 11, which switches to the O state, and the signal from its zero output goes to the installation inputs of the code counter 7 and the input trigger 9, which switches to the O state. The device comes to the ready state to receive regular information from the subscriber.

The introduction of new elements allows the computer to interface with remote devices that have parallel information output, for example, instrumentation devices. The greatest effect is achieved when the input information is organized within the format of the input word in the form of a personal code 1-2-4-8 or In this case, when transmitting four information bits accompanied by a control code in each parcel, identification and ordering of the receive information in a computer is greatly simplified,

Claims (1)

Invention Formula A device for interfacing a subscriber with a communication channel, comprising a synchronization unit, a recording unit, a mode setting unit, a switch, a transceiver, an amplifier, the information output of the amplifier being the output of the device for connecting to the communication channel, while the information input of the amplifier is connected to information the output of the transceiver, the output of the mode of operation of the mode setting block is connected to the input of the mode of operation of the transceiver, the group of information inputs of which are connected to the group of information outputs of the switch The group of address inputs of which is connected to the group of address outputs of the mode setting unit, the synchronization input of which is connected to the first synchronization output of the synchronization unit, the second synchronization output of which is connected to the synchronization input of the transceiver, the recording input of which is connected to the recording output of the recording node, the first starting input of which is connected to the first permitting the output of the block. task mode, about t l and - 0 5 About Q p, five This is due to the fact that, in order to verify the reliability of the transmitted information due to the hardware partitioning of information into separate blocks with its control code, a buffer register, a code counter, an input trigger, a recording trigger, two AND elements, and two NAND elements are entered into it two delay elements, where the group of information inputs of the buffer register forms a group of device inputs for connecting to a group of information outputs of the subscriber, the input trigger trigger input is the device input for connecting to the gate output subscriber, while the readiness output of the transceiver is connected to the input of the first delay element, with the information input of the input trigger, with the counting input of the code counter, with the input of the first AND element, with the first input of the first NAND element, the output of which is connected to the first control of the switch input , the second control input of which is connected to the output of the second element I, the input of which is connected to the second decoupling output of the mode setting block and to the second input of the first AND-NOT element, the first group of information inputs of the switch Ator is connected to a group of information outputs of the buffer register whose recording input is connected to zero you-: input trigger stroke, unit output, whose stroke is connected to the input of the second delay element, the output of which is connected to the single input trigger of the recording, the unit output which is connected to the first the input of the second NAND element, the second input and the output of which are connected respectively to the output of the first delay element and to the second start input of the recording node, the zero input of the recording trigger is connected to the output of the first element I, c oup input of which is connected with a group of second AND input, a second switch group of information inputs and a group code counter outputs, adjusting input coupled to edinich1 th input trigger input and a zero output recording trigger Editor A, Ogar .i Compiled by S. Pestmal Tehred A. Kravchuk CorrectorN. Borisov Order 5542/51 Circulation 668 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Subscription