SU1647615A1 - System for signalling the operation of spatially distributed objects - Google Patents

Abstract

This invention relates to the field of automation, in particular to systems. for signaling the operation of geographically distributed objects, and can be used in automated systems for managing priorities of geographically distributed objects of the automated control system. The aim of the invention is to increase the reliability of the system. For this, the system containing two registers, two decoders, two delay elements, four groups of AND elements, two groups of triggers, the OR element, a group of OR elements and an indicator, introduced four groups of OR elements, groups of And elements, and two groups of groups And elements, block of groups of elements And, five groups of elements of delay, fixed number registers, number changing registers and indicator registers. The system allows to redistribute (adjust) the ranks of objects, and accordingly, to signal the operator about the work of geographically distributed objects, thereby increasing the reliability of control, which is determined by the presence of a stable sequence of objects of control of the ACS for accepting the functions of the control object. 1 hp f-ly, 5 ill. .c $ (I'm with

Description

The invention relates to automation, in particular, to systems for signaling the operation of territorial distribution objects, and can be used in automated priority management systems of geographically distributed objects of automated control systems.

The aim of the invention is to increase the reliability of the system.

Figure 1-3 shows the functional diagram of the system; in fig. 4 - synchronization unit; Fig. 5 shows timing diagrams explaining the operation of the synchronization unit.

The system contains an input register, ready register 2, fixed number 3 registers, number 4 change, indicator 5, ready decoder 6, address decoder 7, rank trigger group 8, trigger group 9, OR element 10, OR element groups 11-14, block groups of elements OR 15, groups of elements OR 16, groups of elements AND 17-21, blocks of groups of elements AND 22 to 23, element 24 of delay,

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groups of delay elements 25-28, delay element 29, group of delay elements 30, indicator 31, synchronization unit 32, groups 33 and 34 of informational inputs, group 35 of address inputs, control inputs 36 and 37, and control output 38.

The synchronization unit 32 is made of triggers 39, 40 and 41, a pulse generator 42, a counter 43, elements AND 44-50, elements OR NOT 51, elements NOT 52 and 53, delay elements 54-56.

The system works as follows.

A complex ACS for control, as a rule, provides for the use of several control objects, one of which is control, and the rest perform the functions of standby, ready to take control upon changes in the situation.

The continuity of control upon leaving the control facility can be ensured by the timely transfer of control functions from one control object to another. To solve this problem, the sequence of inclusion of each control object into the control loop is defined. It is advisable to set such a sequence in the form of a ranking of objects, assigning to each control object a corresponding priority (rank).

The system can be divided into the following cycles; preparation of the system to work. / installation of the system in the initial state, initial loading of the system), system operation (receiving and processing received messages, updating the ranks of objects in accordance with received messages, issuing information about the ranks of objects to the display unit 31, preparation system to the new cycle of adjustment of ranks).

The system is reset to its initial state automatically after powering up the system via reset circuits connected to the corresponding inputs of the elements directly and through the OR elements, if it is necessary to connect the reset inputs through which the elements are also reset during the operation of the system.

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20

25 0 ,,

0 45

50

55

Circuits of the automatic installation of the system are not shown in the initial state.

Before starting work, the operator of each object on his console (not shown in the drawings) dials the number codes of all objects in accordance with the priorities assigned to them. These codes, through information inputs 33, are written in accordance with the rank, the code of which is fed through address inputs 35 to address decoder 7, to fixed number registers 3 (each of which is fixedly fixed), which are previously reset by a signal from control input 36 Reset keys on the remote. Object codes are permanently stored in the registers of 3 fixed numbers throughout the entire operation of the system.

All objects of the ACS control are covered by constant functional control. According to the results of monitoring, from each object, at the time allowed for it, messages on the health of this object are sent to the address of the remaining objects. The absence of a message indicates the inoperable state of the object that did not send it. Message circuits are not shown.

All messages received on the object at a certain time interval are stored in the buffer of the communication computer complex (not shown).

By a certain time, the communication computer complex begins to generate pulses, acting on the control input 37 of the system (Fig. 5, a).

The first clock pulse from the control input 37 is fed to the input 57 of the synchronization unit 32 and sets the trigger 39 (Fig. 5, b) to one state. A high potential trigger 39 triggers a pulse generator 42 (FIG. 5, c).

The first pulse from the output of the generator 42 pulses through the element 44 and 44 (Fig. 5, d) is fed to the counting input of the counter 43, which accordingly changes its state (Fig. 5, d) by opening the element I 45, through which the first impulse from generator 42 to output 58 of synchronization unit 32 (FIG. 5, m), opening groups of elements AND 22, through which object number codes are recorded from fixed number registers 3 to corresponding number change registers 4.

Also, a pulse from the output of the element 45 triggers the delay element 54, which through the trigger 40 generates a control signal (fig. 5, z.i), which is allowed to send messages from the buffer of the computational complex of messages to the system from the control output 38 of the system and opens group of elements and 19.

With each clock pulse arriving at the control input 37 of the system, a message also synchronously arrives at the information inputs 34 of the system. The message from the outputs of the AND elements 19 is written to the input register 1, and then decoded by the ready decoder 6. If the object that sent the message is operational, then the corresponding output of the readiness decoder 6 will have a high potential, which will be written to the corresponding readiness register 2.

The duration of the gating pulse at the output 59 of the synchronization unit 32 (FIG. 5, n) is selected in accordance with the number of objects:

L gr

czg.- Vn

where T "is the period of the following clock pulses at the control input 37 of the system, and n is the number of control objects in the ACS.

After the health information enters readiness register 2, the output clock block 32 (FIG. 50) generates a write pulse that opens AND 17 elements at the corresponding input

and delivers the contents of register 2 of the ready-first element 25 of the delay through

via the inputs of the corresponding elements OR 11 to the installation inputs of the corresponding 8-point triggers.

A write pulse is formed at the output of the element 46, to one input of which a pulse is output from the generator's generator 42 pulses, and to the others - high potentials from the output of the element HE 52, from the output of the counter 43 (figure 5, e) and from the inverse output trig - Hera 41.

Trigger 8, to the setup inputs of which signals of a logical unit are received from the corresponding bits

the first element OR 13 sets the second trigger 8 to zero. In addition, the pulse from the first output of the first delay element 25 triggers the second delay element 25 through the OR element 12. The pulse output of the second delay element 25 opens the second element 2 through which signal of the logical unit is rewritten from the third three hera 8 to the second trigger 8, after the impulse from the second output of the second delay element 25 the third trigger 8 is set to the first

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readiness register 2, at their outputs, form single potentials, the shift of the signals of a pogical unit from the subsequent triggers 8 to the previous ones is effected by clock pulses, which are generated at the output 61 by the synchronization unit 32 (FIG. 5, p). The number of pulses is n - 1.

The write pulse from the output of the AND 46 element triggers the delay element 55 (FIG. 5, k), which controls the trigger 41, through which a signal is formed (FIG. 5, L), the opening element AND 47, through which n - 1 shift pulse arrives on the output 61 of the block 32 synchronization.

The duration of the strobe in this case is calculated as follows;

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4, V - 1) where Tu is the period of the following impulses;

n - the number of objects. The first pulse from the output 61 of the synchronization unit 32 passes through the first element AND 18 of the group and sets the trigger 9 to one state, thereby closing the first element And 21 to pass the pulse from the output of the first delay element 26. In addition, a pulse from the output of the first element 18 starts the first delay element 25, the pulse from the first output of which opens the first element 20 of the group through which the high potential from the direct output. the second trigger 8 is fed to the input of the first element OR tl and then to the setup input of the first trigger 8, setting it to one. Impulse from the second exit

five

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. first delay element 25 through

the first element OR 13 sets the second trigger 8 to zero. In addition, the pulse from the first output of the first delay element 25 starts the second delay element 25 through the OR element 12. The pulse output of the second delay element 25 opens the second element 20, through which the signal of the logical unit is rewritten from the third flip-flop 8 to the second flip-flop 8, after which a pulse from the second output of the second delay element 25 triggers the third flip-flop 8 to the first connection. This will rewrite the signals of the logical unit from the subsequent triggers 8 to the previous ones, and in the last trigger 8 will be recorded the signal of the logical zero.

However, the pulse from the output of the first element AND 18 through the first elements OR 15 and the delay elements 30 sets the first register 4 number changes to the zero state, and through the delay element 27 opens the corresponding elements AND 23 groups through which the object number from the second register 4 The number change is rewritten to the first number change register 4, then the second number change register 4 is set to zero, and so on.

In the case when the input of the first trigger of rank 8 from the register of readiness 2 received a signal of a logical unit, and the input of the second - zero, in subsequent triggers of rank 8, starting with the third, the signals of the logical unit are recorded, on the inverse outputs of the first and second triggers 8 rank are formed respectively low and high potentials. Therefore, the first element And 18 is closed at the corresponding input, the second element And 18 is open. The first clock pulse arriving at this point in time at the output of the first element And 18 does not pass, and the delayed delay element 25 through the open high potential from the inverse output of the trigger 9 element And 21 at the input of the second element And 18. Formed at the output of the second element And 18 the pulse sets the trigger 9 to one state, closes the second element AND 21 for the passage of the pulse delayed by the second delay element 26 and, in addition, through the OR element 12 and the second delay element 26, the cat delay time The first output is not less than the sum of the delay time of the delay element 26 and the duration of the clock pulse, is fed to the input of the second element AND 20 and rewrites the contents of the third rank trigger 8 through the input of the corresponding element 11 of the second trigger 8 rank, thereby shifting the register 2 information readiness one bit to the left (zero excluded).

0

five

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five

thirty

35

40

45

50

55

In this case, the second trigger 9 is set to the zero state with a high potential from the direct output of the second trigger of rank 8. The impulse from the second output of the second delay element 25 goes through the corresponding element OR 13 to the input of the third trigger of rank 8, the drive last to the zero state, and from the first output also through the corresponding elements OR 12 and delay elements 25 to the input (corresponding to a) element 20, rewriting the contents of the subsequent trigger of rank 8 to the previous one, etc.

However, the pulse from the output of the second element AND 18, as a zero pulse, through the second element OR 15 and the second delay element 30 arrives at the return input of the second register 4 number change, erases its contents, and is delayed by the first delay element 28 through the OR element 16 enters the second inputs of the corresponding elements AND 23, rewriting the contents of the subsequent register 4 number changes through the other inputs of the elements OR 14 to the previous one (in this case the second), and through the third element OR 15 and the third delay element 30 as impulses Lens zeroing at the input of the subsequent (third) register 4 number changes, erasing its contents, etc.

Thus, the first clock pulse of the packet eliminates the first zero of the ready register 2 erases the code of the object number corresponding to the register of the ready register 2, in which this zero is fixed and shifts the rest of the information in rank triggers 8 and number change registers 4 by one bit to the left (one readiness register bit 2 corresponds to the code of the number of one object), thus completing the first clock cycle of the shifts.

The second clock pulse from the output 61 of the synchronization unit 32 removes the second zero in the ready register 2 and shifts the information in rank 8 triggers in the number four from the subsequent to the previous registers, thereby determining the second clock shift.

The batch of pulses eliminates all the zeros of the readiness register 2 and compresses the information in TriG16.

Herah 8 rank and registers 4 shift numbers to the left.

After the burst clock pulses eliminate all zeros, and hence the codes of object numbers that have not sent the message, and have shifted all the information to the left, the synchronization unit 32 at its output 62 generates an IMPULSE Zero of registers

dictator 5 (Fig. 5, p). This pulse is formed at the output of the element 48, to one input of which a pulse is fed from the output of the generator 42, to the others - potentials from the outputs of the counter 43.

To record the updated information from the shift registers 4 to the corresponding indicator registers 5 of the indicator, the synchronization unit 32 generates a write pulse, which from output 63 (figure 5, c) goes to the control inputs of the record of the indicator registers 5 and rewrites the contents of the registers 4 number changes in the corresponding registers 5 of the indicator. A write pulse is generated at the output of an element 49, to one input of which a pulse arrives from the generator 42, to the others - high potentials from the outputs of the element HE 53 and counter 43 (figure 5, g) Updated information of the indicator registers 5 in the form of a ranking table is displayed on the indicator 31. At the same time, the numbers of ranks are highlighted with the indicator 31 on a constant basis, and only the numbers of the objects corresponding to the corrected ranks change.

At the end of the rank adjustment cycle from the output 64 of the synchronization unit 32 (FIG. 5, t), a reset pulse is generated, which zeroed the ready register 2, the rank 8 triggers and the number changing registers 4. This pulse is formed at the output of the element 50, to one input of which a pulse is sent from the generator 42, to the others - high potentials from the outputs of the counter 43. In addition, from the output of the element 50, a reset pulse through the delay element 56 (figure 5) goes to return inputs trigger 39 and counter 43, setting them to the zero state.

Claims (2)

1. A system for signaling the operation of geographically distributed objects, comprising an input register, 15 0 Q s 0 5 0 s 0 5 g the outputs of which are connected to the inputs. the first decoder, the first delay element, the output of which is connected to the reset input input register, the first group of elements And the outputs of the first, second and third elements and which are connected to the first inputs of the same trigger of the first group, the second group of elements And, the first inputs of which are combined, the third and fourth groups of AND elements, the ready register, the second decoder, the first group of OR elements, the second group of triggers, the second delay element, the OR element, and an indicator that, in order to increase the reliability system, the synchronization block, fixed number registers, number change registers, indicator registers, block, OR groups of elements, first and second blocks of AND, second, third, fourth and fifth groups of OR, pen and the sixth group of elements, And, the first, second, third, fourth and fifth groups of delay elements; the first output of the synchronization unit is the control output of the system and is connected to the first inputs of the AND elements of the third group, the second inputs of which are the first group of information inputs the system, the input of the synchronization unit is the first control input and is connected to the third inputs of elements AND of the third group, whose outputs are connected to the information inputs of the input register, the outputs of the first decoder are connected to the inputs of the OR element and to the information inputs of the ready register, the outputs of which are connected to the second the inputs of the elements of the same name AND the second group, the outputs of the first, second and third elements And which are connected to the first inputs of the elements of the same name OR the second group, the outputs of which are connected to the first inputs of the same trigger of the second group, the output of the fourth element And the second group is connected to the first input of the fourth trigger of the second group, the first outputs of the trigger are connected to the first inputs of the same elements of the first group, the second outputs of the first, second and third triggers of the second group are connected to the second inputs of the same trigger of the first group, the second the outputs of the second, third and fourth triggers of the second group are connected to the first inputs of the first, second and third elements of the fourth group, respectively, the outputs of which are connected to the second inputs of the OR elements of the same name of the second group, the outputs of the AND elements of the first group are connected to the first inputs of the same elements of the third group The outputs of which through the same-delay elements of the first group are connected to the reset inputs of the same-named change number registers, the outputs of which are connected to the information inputs of the same The indicator registers, the outputs of which are connected to the indicator groups of the indicator inputs of the same name, the output of the first element AND of the first group are connected to the input of the first delay element of the second group, the outputs of the second and third episodes of AND the first group are connected to the first inputs of the first and second elements OR of the first group, respectively. which are connected to the inputs of the second and third delay elements of the second group, respectively, the first outputs of the delay elements of the second group are connected to the second inputs of the same elements And the fourth group, the first outputs of the first and second delay elements are connected to the second inputs of the elements of the same name OR of the first group, the second outputs of the delay elements of the second group are connected to the first inputs of the elements of the same name OR the fourth group, the outputs of which are connected to the second inputs of the second, third and fourth triggers respectively the second group, the second output of the synchronization unit is connected to the second input of the first element And the first group and to the input of the first delay element of the third group, the outputs of the triggers The first group is connected to the first inputs of the elements of the same name and the fifth group, the outputs of the first and second elements and which are connected to the second inputs of the second and third elements of the first corpse and the inputs of the second and third elements of the third group, respectively, the output of the third element of that group is connected to the second input of the element AND the first group, the outputs of the delay elements of the third group 0 five 0 five 0 five 0 five dinene with the second inputs of the same elements of the fifth group, the third output of the synchronization unit is connected to the first input of one of the elements of the second group, the fourth output of the synchronization unit is connected to the reset input of the ready register, with the second input of the first trigger of the second group, with the second inputs of the OR elements the fourth group and with the second inputs of the elements OR of the third group, the fifth output of the synchronization unit is connected to the reset inputs of the indicator registers, the sixth output of the synchronization unit is connected to the inputs of the register recording The indicator, the seventh output of the synchronization unit is connected to the first inputs of the elements And groups of the first block, the information inputs of the second decoder are the system's address inputs, the outputs of the second decoder are connected to the fixed-number registers of the same name, the outputs of which are connected to the second inputs of the And blocks of the same block of the first block , the outputs of the first, second and third groups of which are connected to the first inputs of the elements of the OR groups of the same name, the outputs of the groups of the block of the elements of the OR are connected to To the operational inputs of the same shift number registers, the outputs of the second, third and fourth shift number registers are connected to the first inputs of the AND elements of the first, second and third groups of the second block, the outputs of which are connected to the second inputs of the OR elements of the same group of the block, the outputs of the AND elements of the fourth group of the first the block is connected to the information inputs of the fourth shift register, the output of the first element And the first group is connected to the input of the first delay element of the fourth group, the output of which is inn with the second inputs of elements AND of the first group of the second block, with the third input of the second element OR of the third group and through the second delay element of the fourth group connected to the third input of the third element OR of the third group and to the first input of the first element OR of the fifth group, which through the third element the delay of the fourth group is connected to the third input of the fourth element OR of the third group and to the first input of the second element OR of the fifth group, output which is connected to the second input of the elements AND of the third group of the second block, the output of the second element AND of the first group through the first element of the fifth group is connected to the second input of the first element OR the group and to the fourth input of the third element OR of the third group, which through the second element the delay of the fifth group is connected to the second input of the second element OR of the fifth group and to the fourth input of the fourth element OR of the third group, the output of the third element AND of the first group through the second delay element connected to the third to it the input of the second element OR of the fifth group and to the fifth input of the fourth element OR of the third group, the output of the first element OR of the fifth group is connected to the second inputs of the AND elements of the second group of the second block, the output of the OR element is connected to the input of the first delay element, reset inputs the fixed numbers are combined and are in the second control input of the system, the information inputs of the fixed number registers are the second group of information inputs. 2. Pop-up system 1, characterized in that the synchronization unit is made of a pulse generator counter, three triggers, seven ele the elements AND, the element OR NOT, two elements NOT and three elements in the delay, the first input of the first trigger is the input of the synchronization unit, the output of the first trigger is connected to the input of the pulse generator, the output of which is connected to the first inputs of the elements AND, the output of the first element AND is connected with the first input of the counter, the first output of which is connected to the second Q Q 5 0 five 0 5 The second inputs of the second, third, and fourth elements of AND are not connected via the first and second elements to the second inputs of the fifth and sixth elements, respectively, and the second output of the counter is connected to the third inputs of the third and fifth elements of AND and the first input of the OR element -NON, the output of which is connected to the third inlet of the second element I, the output of which is connected to the input of the first delay element, the first and second outputs of which are connected to the same inputs of the second trigger, the first output of which is the first output of the sync block and the second is connected to the fourth input of the second element I and to the second input of the first element I, the first output of the third trigger is connected to the third input of the first element I and to the fourth input of the fifth element AND whose output is connected to the input of the second delay element, the first and the second outputs of which are connected to the same inputs of the third flip-flop, the second output of which is connected to the second input of the seventh And element, the output is the second output of the synchronization unit, the output of the fifth And element is the third output of the C block synchronization, the third output of the counter is connected to the second input of the element OR NOT, to the third input of the sixth AND element and to the third input of the fourth AND element, the output of which is the fourth output of the synchronization unit and through the third delay element connected to the second inputs of the first trigger and counter, the outputs of the third, sixth and second elements And are the fifth, sixth and seventh outputs of the block, respectively. chronicity. cig { 2 Fig.Z - p p p. p p p p p. pp pp L oS8 about 59 (rig.C. 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