SU1564621A1 - Microprogram control device - Google Patents

Abstract

The invention is intended for use in computing when creating input-output devices, interface equipment, measuring and household appliances. The purpose of the invention is to increase the speed of the device with the multi-functional use of the bits of the memory of micro-instructions and synchronization of the signs of conditions. The device contains a multiplexer, an EXCLUSIVE OR element, a microcommand address generation node, a memory block, buffer registers, the first and second NOT elements, the AND element, the AND-NOT element. The goal is achieved by the fact that the first and second buffer registers, the first and second elements are NOT, the AND-NOT element, and the AND element allow to combine in time the functions of pre-buffering the bits of the microinstruction memory and synchronizing the signs of conditions. 3 il.

Description

The invention relates to computing and can be used to create a wide class of means: input-output devices, interface equipment, measuring and household appliances.

The purpose of the invention is to increase the speed of the device with multi-functional. use of bits of the memory of microinstructions and synchronization of the signs of conditions.

FIG. 1 is a functional block diagram of a firmware control device; FIG. 2 - time diagrams of the device; in fig. 3 - time diagrams of the device during the conditional transitions.

The device (Fig. 1) contains a multiplexer 1, an EXCLUSIVE OR 2 element, a device synchronization input 3, a microcommand address generation unit (UFAM), a microcommand memory unit 5, a decoder group 6, a microcommand memory 5 output 7, an output 8 micro-operations of the device, output 9 fields of logical conditions and operation code of block 5 of microinstructions memory, output 10 of the first decoder of group 6 of decoders, first buffer register 11, second buffer register 12, first element NOT 13, second element NOT 14, element NAND 15, element 16 and exit 17 the first bit of the first buffer register 11,

: exit 18 logical conditions of the device, reset input 19 (set to O) of the device, output 20 seconds per second at the first bits of the first buffer register, output 21 (P-H) -th bit of the First buffer register, output 22 ( P + 2) bit of the first buffer (register, output 23 of the first to (P-1) -th bit of the second buffer generator, output 24 (P +) - of the second bit of the second buffer register, input ± 5 multiplayer control 1, the gate 26 of the multiplexer 1 gating, the inversion flag 27 of the condition of the logic conditions of the myco-co-: ande memory block, the input 28 from the first time –– the first poisons th buffer register

: Movements 29 and 30 (P + 2) -th and (P + 1) -th

the gaps of the first buffer register

the input 31 of the reset of the first buffer registrar.

The features of the device include:

The control memory pads are sub-m), which are connected to the multiplexer of conditions, the whole polarity control, the source address selection scheme of the following microcommand and control: stack operation, are not used when addressing the transition address, when controlling external circuits leads to an increase in the amount of hardware that expands the control memory lol width and an increase in the design capacity in terms of firmware development.

In various equipment, where the proposed device is applicable, it is possible to connect signals of conditions asynchronous with respect to the device clock frequency. When analyzing their pre sync faults, races occur in the stack control scheme and the choice of address source, which leads to device malfunction. conditions before multiplexing, i.e. beyond the device, associated with hardware costs, the amount of which depends on the number of condition signals being analyzed, the implementation of the requirement for the multifunctional use of the discharge field of the microinstructions memory block necessarily leads to a time delay, since it is necessary to organize

0

with

five

0

five

0

New buffering of constants read from it.

The synchronization inside the device of signal conditions, asynchronous with respect to its clock frequency, further increases the time delay of the device, i.e. reduces its speed.

Node 4 can be implemented on a chip 1804VU1.

The device operates in two modes: either it performs a sequential sampling of microcommands (main mode), or it implements a conditional (unconditional) transition.

The operation in one mode or another is determined by the signals set by the second buffer register 12 on the inputs of the UVAM operation code. Thus, the signals 23 select as the source of the address of the following microcommand or the internal microcommand counter (SMC), or the UVAM address register, or the internal UVAM stack, or the data bus connected to the UVAM inputs determine the operation mode with the stack. In the basic mode of bit 7 of block 5 of memory of microinstructions, gated with a clock frequency, one or several microoperations 8 are produced in a group of 6 decoders; which, accompanied by bits 9 of the firmware memory, are output to external devices. Microoperations 8 write code constants of bits 9 in the registers of external devices in accordance with a certain algorithm, as a result of which the control function is performed. In this mode, the second buffer register 12 sets signals corresponding to the disabled stack to the control inputs of the UFAM and selects the QMS as the source addresses of the next microinstruction.

The operation of the second mode is performed when it is necessary to select a microcommand to be executed that is not a regular command of the sequence, with or without dependence on the condition. This transition occurs within two clocks of the synchronization frequency. In the first cycle, in the group of 6 decoders, a micro-op-, chi 10 is produced, connected to the first buffer register 11. Simultaneously

 bits 9 of the micro-instruction memory block select the necessary condition in multiplexer 1, select its required polarity in element 2. A part of bits 9 of the micro-instruction memory block is connected to the first buffer register 11. They contain information about the proposed source of the transition address and the stack operation mode UFAM. Through micro-operation 10, the selector condition is synchronized in the first buffer register 1 and, depending on its polarity, the information-carrying bits of the microinstruction memory are pre-memorized (or not stored). However, after the first clock cycle, the outputs of the second buffer register remain unchanged. Actually the transition itself is carried out. after the end of the second cycle, when the second buffer register 12 sets on the UFAM inputs the code of the new source of the microcommand address. During the second clock of frame 9, the microinstructions memory block must contain the transition address, if it is envisaged to select the internal address of the UVAM as the address source. As can be seen from the functional diagram, the bits of the 9 microcommand memory blocks are connected to the inputs of the internal register of the UFAM address. Writing to this register is always allowed. However, in the mode of consecutive sampling of micro-instructions, the addresses of the bit 9 of the memory block of micro-commands recorded in the register do not carry any functional load.

At the end of the second clock cycle, the second buffer register 12 sets on its outputs signals corresponding to the sequential sampling mode. Then everything repeats. The operation in both modes is explained by the timing diagrams in FIG. 2

Thus, bit 9 of the microinstructions memory unit is used in the three main functions of the microprogrammed control unit separated in time. They participate in the management of external devices, the preparation of the source of the transition address, depending on the condition, in the formation of the transition address itself. In this way, multifunctional use of the bits of the microinstruction memory block is realized.

0

Before operation, the device is reset with the Reset Negative Polarity signal. This signal passes through the element And 16, arrives at the installation input of the register 11 and zeroes its outputs. The closest positive clock speed difference between register 11 is rewritten into register 12. As a result, UFAM starts to operate in the sequential mode of sampling of micro-instructions with the stack disabled. Suppose that there is a need for a conditional transition. In the first cycle, bits 9 of the microinstructions memory block work as follows. The bits 25 of the logical conditions from field 9 select in the multiplexer 1 the desired signal condition, the bit 26 of gating the multiplexer from the logical conditions unlocks this multiplexer 5 (it blocks it at an unconditional transition), bit 27 adapts the selected signal of the condition so that his confirmation was negative polarity. Bit 28 of code 0 operation carries information about the choice of the source of the transition address and the operation mode of the stack in case the condition signal is confirmed. In the same tact, a group of 6 decoders generates a micro-operation 10. Suppose that the selectable signal of the condition is not acknowledged. Then a high potential appears at the input 29 of the register 11 at the first clock (a high level is connected to the input 30 of the register 11 at the first clock). Micro-op - i qi 10 writes down signals connected to the first inputs information, including the condition signal, by a positive differential to the register 11, synchronizing it, However. the potential of the high level detected at the output 23 after inversion in the element 14 NOT and the passage element AND 16 again sets the register 11 to the initial state. Register 11, once it has been set to its original state, recovers a high potential at its installation input. In the second clock cycle, the outputs of register 11 are rewritten to register 12, but no changes are made at the inputs of the UFAM.

five

0

five

0

five

The conditional differential is not valid. The firmware manager still operates in sequential mode with the stack disabled. FIG. Below is a time diagram of a conditional transition for cases with an unconfirmed condition signal.

Assume that the selectable signal | L conditions is confirmed and the transition to the contents of the internal register of the UFAM address is presumed. Then micro-operation 10 on the input 23 of register 11 records a low potential. In this case, register 11 is not set to its original state. Outputs 17 and 20 retain the recorded code for the UVCAM. In line 21, a high level is set. The same potential is set at the second input of element 15. In the second cycle, the outputs of the register And are rewritten into register 12, and the bits; 9 microinstructions memory blocks containing the transition address are written to the UVAM address register. In the third cycle, the source of the address of the selected micro-command is already the UVAM address register (with the information entered in it). I

The conditional transition was. Immediately after the end of the second clock cycle, a negative polarity signal appears at terminal 15, since the H3i outputs of this element are prepared with positive potentials.

As a result, a signal passes to the setup input of register 11, which sets it to its initial state. Output 21 assumes a zero value, then the signal 31 restores its positive polarity. FIG. 36 shows a time-conditional transition diagram for a case with a confirmed condition signal.

The peculiarity of the device operation is that the synchronization and analysis of the condition condition occur simultaneously with the preliminary buffering in the first buffer register of memory blocks of the microcommand, which eliminates additional time delays for the implementation of these functions and increases the speed of the device operation.

0 5 0

d 5

0 e

five

Claims (1)

Invention Formula A microprogram control device containing a multiplexer, an EXCLUSIVE OR element, a microcommand address generation unit, a microcommand memory block, a group of decoders, and the outputs of the logic conditions, the condition analysis sign and the inversion sign of the microcommand memory block conditions, respectively, are connected to the control gate input multiplexer and with the first input of the EXCLUSIVE OR element, the outputs of the fields of logical conditions and the operation code of the microinstructions memory block and the signs of the analysis of conditions and the inversion of conditions with are connected to the first information input of the microcommand address generation unit and are the first information output of the device, the output of the microoperations micro-operations field is connected to the information inputs of the group decoders whose outputs are the second information output of the device, the multiplexer output is connected to the second input of the EXCLUSIVE OR element , the information input, the multiplexer is connected to the output of the logical conditions of the device, the second information input of the node forming the address of the microcommand with the input of the operation code of the device, the synchronization input of the microcommand address generation node and the group decoder gating inputs are connected to the device synchronization input, the installation input of the microcommand address formation node O is connected to the device installation input, characterized in that, in order to increase speed devices, due to the combination in time of the operations on buffering the microinstructions read from the memory block with synchronization and analysis of the signs of conditions, the first and second buffer registers are entered into it The first and second elements are not, the AND-NOT element, and the element, and the output field of the operation code of the microcommand memory block is connected from 1st to (where P is the code of the operation code) information inputs of the first buffer register, first output the first buffer register is connected to the input of the first element The NOT whose output is connected to the first information input of the buffer register, from the second to (P + 2) th output of the first buffer register, is connected to the second to (P + 2) information inputs of the second buffer register, from the first to P- th bits of the output of which are connected to the inputs of the operation code of the node of the formation of the microcommand address (P + 1) th information input of the first buffer register connected to the potential of the logical unit of the device, (P + 1) th output of the first buffer register connected to the first input of the element NAND, the output of the EXCLUSIVE OR is connected to the (P + 2) -th information input of the first buffer register (P + 2) -th output of the first buffer register connected to the input of the second element NOT, the output of which is connected to the first input of the element AND the output of which is connected to the installation input in O of the first buffer register, the first output of the first group decoder is connected to the synchronization input of the first buffer register, the output of the NAND element is connected to the second input of the AND element, the third input of the AND element is connected to the device installation input, the sync input. tion of the second buffer register connected to an input device synchronization. kri f t ± 26 W rf-lh t AND 1L W - Yo JЈ- W Clock Frequency - LOEDPEE /// H 1, J. Bits 9 ijSM .. I Wltbff And "0 1 G 11-I - 1 Outputs gpynnul u u u l decoders and i-j-- "-" - Microoperations 8№ ° Jura Microoperations S Fig 2. 9 and 2S SHKSH #, $ -I Fi & .1 -40 ijSM .. Fig 2.