SU1215133A1 - Three-channel redundant storage - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices for use in control control systems and the like. The purpose of the invention is to increase the reliability of the device. Each channel of the memory of the device dego contains a signal conditioner, AND elements, triggers, switches, majority elements, a memory block, a shift register, and the UNEMINABLE element. The device implements the procedure of background majorization of the contents of the memory device, consisting of the following steps: reading the contents of the same in all channels of the cell of the memory unit to the shift register, shifting the contents of the shift register towards the higher bits, majorizing on the majority the element and the synchronous recording of the contents of the Register register to the initial cell of the memory block. 2 Il. to О1 со со

Description

one

The invention relates to computing, in particular, to storage devices.

The purpose of the invention is to increase the reliability of the device.

Figure 1 shows the functional diagram of one of three similar channels of the device; Fig. 2 is a timing diagram for explaining the operation of the device.

The proposed device contains in each channel (FIG. 1) a driver 1 of signals, the first element I2 of the first element, triggers 3-5 from first to third, the first 6 and second 7 switches, elements 8-10 from second to fourth, the first majority element 1I , memory block 12, shift register 13, second major element 14, fourth 15 and fifth 16 flip-flops, information register 17, element UNCRETENESS 18, sixth flip-flop 19, element 2I-2I-2IL-HE20 and seventh flip-flop 21.

In Fig. 1, address 22, informational 23 and 2D and 25 control inputs of the device, inputs 26 and 27 and output 28 of the channel control signal exchange, inputs 29 and 30 and output 31 of the channel information exchange, information 32, indicator 33 and control are indicated 34 device outputs, inputs 35 and 36, and channel synchronization output 37, one of the direct outputs 38-42, the other outputs 43, one of the direct outputs 44, and the inverse outputs 45-47 of the signal conditioner 1.

Figure 2 shows the signals at the outputs 38-42 from the second to the sixth, the signals 43..1, 43.2, 43 (k-2), 43 (k-1) on the seventh and subsequent outputs and the signals 44 on the K m output ( where k is the number of outputs), the driver 1 signals. In Fig. 2, signal G14 is also indicated at the direct output of trigger 3, the clock signals 49 at the output of the element 10, the control signals

50 at the output of the element And 8 signals

51 on the control inputs of the switches 6 and 7, the operation mode signals 52 generated at the output of the element 20, the request request signals 53 at input 25, the operation mode signals 54 at input 24, and the signals 55-57 at the outputs of the triggers 5, 16 and 21, respectively.

In Fig. 1, a signal conditioner is indicated, which contains a counter, the value To of which is determined

to

20

25

1215133

the address resolution of block 12 in such a way that the number of bits of the address i of block 12 is equal to (K-6).

The device works as follows.

The time setting element of each channel of the device is shaper 1 (FIG. 1), the main element of which is a K-bit counter. The synchronization of the formers 1 of the three channels of the device is provided via the inputs 35 and 36 and the output 37, as a result of which all signals are synchronous in each channel of the device. The reliability of storing information in block 1-2 of each channel is enhanced by introducing a background majorization procedure for the contents of the entire memory.

This procedure consists of the following steps.

In all the channels of the device, the contents of the same cell of block 12 per register are synchronously read. The equality of the cell addresses in all channels is ensured by the synchronism of the driver 1.

After receiving the information on register 13, its contents are shifted towards the higher bits as many times as the cell width of block 12. At the same time, the high-order bits that are moved are majorized on 35 element 11 and returned to register 13 to the lower bits. Therefore, after a complete shift of the contents of the register 13, the initial weights of all the bits do not change, but 40 the contents of the registers 13 of all three channels will be the same.

Then, in all channels, the contents of the register 13 are synchronously recorded in the initial cell of block 12. 45 The indicated majorization procedure works independently of the access to the charger from the external interface via inputs 22-25.

If when accessing the memory from the external interface, one of the channels fails and the contents of block 12 of one of the channels differ from the other two, then the procedure of majorization will restore the information 55 in block 12, thereby increasing the reliability of information storage.

Access to the memory from the external interface is allowed only in moments.

thirty

when the signals at the output 39 are equal to O of the reading and writing reversal from the side of the majoritarian procedure, determined by the time interval during which the signal 51 generated at the output of the element I9 is equal to 1,

During this interval, the switches 6 and 7 switch to the block 12 the contents of the outputs 43 of the former 1 of the register 13.

When accessing block 12 from the side of the majorization procedure, when the signal value 42 is 1, the contents of register 13 are written to block 12, and when the signal value is 42, O is read from block 12 to register 13. Reception of information to register 13 occurs by a negative differential signal 38 with a positive value of the signal 50f fig.2J. The write mode (the first positive impulse 52) is initiated by a call from the external interface, and the second positive impulse 52 by a call from the procedure of majorization. The external interface access signals and their processing are presented in Figure 2 by signals 53-57.

To allocate the interval in which information is shifted on register 13, signals 41 and 42 are sent to inputs of trigger 3, and direct and inverse signals 48 are generated at its output (Fig. 2). The shift on the register 13 and the entry on the trigger 15 occurs on the negative differential signal 49.

The trigger 15 records information from the output of the UNEQUALITY element 18, which compares bit-wise information from the output of the register 13 of this channel and from the output of the element P, which majorizes the populated information from the outputs of the registers 13. of all channels. The discrepancy between the information at the inputs of element 18 indicates a failure of information in the channel in question, which causes the trigger 15 to coax. But when the follower bit is majorized due to the feedback entered at the trigger input 15, it is set to the normal reset state, therefore, to store detected A bad situation is set to trigger 19, which is cocked by

each positive signal at the output of the trigger 15, and is reset by a negative differential signal 44 and stores the detected failure to

the end of the current majorization cycle of the contents of block 12. The majoritarian information cycle of the entire memory is determined by the period of operation of the former 1. The signal IAD is

45, a negative level which reads or writes information in block 12.

Analysis of the channel failure is enough to lead on the basis of the analysis

the state of only the inputs and outputs 26-31, 35,36 and 37, which increases the reliability of the device. The processing of requests from the external interface is carried out in the following way.

Signal Appearance The memory request at input 25 is memorized on trigger 4 and, on the leading edge of signal 39, is recorded on trigger 5, the information on the output of which is majority,

It is located on element 14, and on the leading edge of the signal 46 is rewritten to trigger 16, which determines the moment of access to the memory from the external interface. In this moment

at the output of the element 20, a reference mode signal is generated. Trigger 4 is reset by cocking trigger 5, and trigger 5 by cocking trigger 16. The need for preliminary signal replaying The request of the charger on trigger 5 is determined by the need to select a time interval for the majorization of the inversion signal. On the leading edge of the signal

from the inverse output of the trigger 16 the trigger is activated, form a signal. The response of the request at the output 34, which is reset when the signal at input 25 disappears. In addition, a positive signal at the output of the trigger 16, entering the input of the register 17, allows it to receive information from the block 12 on the falling edge of the signal 38 for reading information in the output 32.

Claims (1)

Invention Formula A three-channel redundant memory device, containing in each canape a memory block, a first major element, first and second switches, characterized in that, in order to increase the reliability of the device, a second major element, the first to seventh triggers, are inserted into each channel of the device, shaper of signals, shift register, elements And from the first to the fourth, the element of unequal, information register and the element 2I-2I-2ILI-NOT, and one of the direct outputs of the signal conditioner are connected respectively Respectively to the synchronization inputs of the information and shift registers and the first input of the fourth element And, to the first input of the first element And the clock input of the third trigger, to the second input of the first element And, the first input of the first trigger, the first input of element 2I-2I-2ILI - NOT to the second input of the first trigger, to the clock input of the sixth trigger, one of the inverse outputs of the driver of signals is connected to the first control input of the memory unit, the clock input of the fifth trigger and the first input of the second element respectively And, the output of which is connected to the control input of the shift register, the other outputs of the signaling generator are connected to one of the inputs of the first switch, the output of the first element I is connected to the first input of the third element I, the second input of which is connected to the inverse output of the first trigger, the direct output of which connected to the second input of the fourth element And, the output of which is connected to the clock input of the fourth trigger and the first synchronization input of the shift register, one of the information inputs of which are connected to the outputs of the information register, and the outputs to one of the inputs of the second switch, the output of the third element I is connected to the second input of the element 2I-2I-g2ILI-NOT, the second input of the second element I and the control inputs of the first and second switches, the outputs of which are connected respectively to address and information inputs of a memory block, the outputs of which are connected to the inputs of the information register, the control input of which is connected to the direct output of the fifth trigger and the third the input of element 2I-2I-.2, OR-NOT, the output of which is connected to the second control input of the memory unit, inverse 5, the output of the third trigger is connected to the reset input of the second trigger, the output of which is connected to the start input of the third trigger, the direct output of which is connected to the first input to the second major element, the output of which is connected to the input of the fifth trigger, the inverse output of which is connected to the reset input of the third trigger and clock input 15 the seventh flip-flop, the inverse output of the fourth flip-flop, gera is connected to the installation input of the 1st sixth flip-flop and the reset input of the fourth flip-flop, the trigger input of which is connected to the 20th output of the NEGATIVE element, the first input to The other and other information inputs of the shift register are connected to the output of the first major element, the first input of which and the second input of the UNEMATICAL element are connected to one of the outputs of the shift register, the start inputs of the second and seventh flip-flops are connected to the power bus, the input 30 starts the sixth flip-flop connected to the bus the zero potential, the second and third inputs of the first major element and one of the outputs of the shift register are respectively The 5 inputs and output of the channel information exchange, the second and third inputs of the second inter-element element, and the direct output of the third trigger are respectively the input-output of the exchange. The channel control signals, the first and second inputs and the control output of the signal conditioner are the inputs and output of the channel synchronization, the clock input of the second trigger and the reset input of the seventh trigger are the first control input of the device, the indicator and control outputs and the second control The input of which are, respectively, the outputs of the sixth and seventh trigger and the fourth input of the element 2I-2Y-2OR-NOT, the other inputs of the first and second switches and the outputs of the information register are co5. responsibly address and information inputs and information outputs of the device. VNIIPI Order 908/57 Branch PPTT, Uzhgorod, st. Project, 4 Circulation 544 Subscription