SU1596335A1 - Device for shaping control code by modulo two - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in interface devices of digital computers with external subscribers. The purpose of the invention is to increase the speed of the device. The device contains register 1, register 2 svdiga, trigger 3, elements OR 4, 5, elements AND 6, 7, blocks 8, 9 priority, group N of triggers 10, group N And elements 11-13, group N OR elements 14. Controlled the code is written to register 1. The first priority block 8 allocates the rightmost unit of the code being monitored and, using elements 12, writes the unit to the corresponding register shift register 2. The second priority block 9 allocates the leftmost unit of the code being monitored and through the elements of AND 13 the corresponding trigger 10 is set to one state. The "unit" moves along the shift register 2, accompanied by the appearance of single signals at the zero inputs of the trigger 10. The zero trigger is reset. 10, set to the unit state by the AND unit 13, a single signal is generated at the output 20 of the device, and a control code modulo two is output from the device output 19. The number of ticks needed to form a control code modulo two is equal to the number of bits between the extreme "units" of the code. 1 il.

Description

The invention relates to computer and computer technology and can be used in interface devices of digital computers with external subscribers.

The purpose of the invention is to increase the speed of the device.

The drawing shows a functional diagram of the device,

The diagram shows register 1, shift register 2, trigger 3. OR elements 4 and 5, AND 6 and 7 elements, priority blocks 8 and 9, trigger group 10, AND 11-13 element groups, OR 14 element group, information input 15 device, device setup input 16, device clock input 17, device startup, device control code output 19, device control code generation end output 20, group of elements AND 21 priority blocks 8 and 9, group of elements NOT 22 priority blocks 8 and 9 and input 23 records of the monitored device code.

Register 1 provides storage of a controlled p-bit code, received into the device at input 15.

The priority block 8 is designed to allocate the leftmost unit of the word stored in register 1, and send it through the second group of elements And 12 to the corresponding bit of shift register 2.

The priority block 9 serves to select the rightmost units in the word stored in register 1 and send it through the third group of elements AND 13 to the corresponding trigger 10 of the group.

The first element OR 4, in the unit state of any of the group 10 triggers, allows the clock pulses from input 17 to pass through the first element AND 6 to the clock input of the shift register 2, and when zero, allows the passing through the second element 7 to output 20 generating a control code.

Shift register 2 shifts the unit from the bit in which the first left unit in register 1 is recorded to the bit in which the last right one unit is recorded in register 1. When the unit is shifted, the signals from the outputs of the shift register 2 through the elements of the OR 14 group are successively fed to the inputs of the installation in the O triggers of the 10 group.

The first group of elements AND 11 serves to form single signals through the second element OR 5 to the counting input of trigger 3 when the unit codes in the same bits of register 1 and

register 2 shift in the process of shifting a single code in the register 2 shift.

When the signal is applied to the input 16, the resetting of the triggers of group 10, registers 1 and 2 and trigger 3 is provided.

The signal at input 18 permits the transfer of units from priority block 8 to shift register 2 and units from priority block 9 to the single input of the corresponding trigger 10 of the group. Upon completion of the operation of the device, a control code is generated at output 19.

The device works as follows.

The signal of the initial installation at the input 16 of the device resets the register 1, the shift register 2, the trigger 3 and the trigger group 10. A signal at the input 23 of the recording of the monitored device code is written to the register 1 via the information input 15 of the device, the monitored code is recorded. The priority block 8 defines the leftmost unit in the monitored code, and the priority block 9 defines the rightmost unit. Blocks 8 and 9 priority work the same way.

Consider the selection of the leftmost unit. If the unit is in the leftmost section, it passes to the output of priority block 8 and through the first element is NOT 22.1 to the second inputs of all And 21 elements, passing through them to the output of block 8 priority of other units. If a zero is recorded in the first digit, then it, having passed through the element NOT 22.1, allows the passage of the unit through the first element AND 21.1 if there is a unit at its first input. The signal from the output of the first element And 21.1, having passed through the second element NOT 22.2, closes all the remaining elements And 21 {21.2-21. (N-1)) and so on. Thus, at the output of the priority block 8, the unit of the first left, non-zero bit, passes.

According to the trigger signal supplied to the device input 18, the unit from one of the outputs of priority block 8 is written through the corresponding AND 12 element of the second group to the shift register 2, and the unit from one of the outputs of priority block 9 through the corresponding AND 13 element of the third group sets the trigger 10 the group corresponding to the discharge of the code being monitored, in which the last one to the right is written, is set to one. In this case, the output signal of this trigger through the first element IL AND 4 opens the first element AND 6 and the clock frequency signals from the input 17 of the device arrive at the clock input of the shift register 2. Unit shift to

shift register 2 occurs until the output signal from the corresponding bit of register 2 shift is set through the OR element of the 14th group to the zero state of the trigger, which was in the unit state. At the same time, at the output of the OR 4 element, a zero value of the signal is established, which prohibits the passage of clock signals through the AND 6 element from the clock input 17 of the device. At the same time, the element AND 7 is opened and at the output 20 of the device, a signal of the end of the formation of the control code appears. The device is ready to receive the next code.

In the formation of the control code at the output 19 takes part in the process of shifting the unit in the shift register 2, the first group of elements 11, each of which compares the contents of the corresponding bits of register 1 and shift register 2. If there are units in the same bits, the OR 5 element on the counting input of the trigger 3 is given a control signal, which transfers the trigger 3 to the opposite state. After the completion of the unit shift in the shift register 2, trigger 3 contains the control code that is output to the device output 19.

Thus, the proposed device provides for the formation of a control code without sending the controlled code to the shift register.

Claims (1)

Invention Formula Device for modifying the control code modulo two, containing a register, shift register, two-block priority, two AND elements, two OR elements and a trigger, with the first input of the first AND element and the direct input of the second element AND connected to the clock input of the output, output the first element OR is connected to the second input of the first element AND and the inverted input of the second element AND whose output is the output of the end of the formation of the control code of the device, the output of the first element AND is connected to the clock input of the shift register, The register, shift register and zero trigger input inputs are connected to the device setup input, the trigger output is the control code output of the device, the register information input is the device information input, the register clock input is the input of the monitored device code, characterized in that in order to increase the device speed, a group of triggers is entered into it, three groups of AND elements and a group of OR elements, and the register outputs are connected to the first inputs of the corresponding AND of the first group and the corresponding information inputs of the first and second priority blocks, the outputs of the first priority block are connected to the first inputs of the corresponding AND elements of the second group, whose outputs are connected to the corresponding information inputs of the shift register, the outputs of which are connected to the second inputs of the corresponding And elements groups and the first inputs of the corresponding elements OR groups, the second inputs of which are connected to the installation input of the device, the outputs of the elements AND the first The second group is connected to the inputs of the second OR element, the output of which is connected to the counting trigger input, the outputs of the OR group elements are connected to the zero inputs of the corresponding group triggers, the forward outputs of which are connected to the corresponding inputs of the first OR element, the output of the second priority block is connected to the first inputs of elements of the third group, the outputs of which are connected to the single inputs of the corresponding group triggers, the second inputs of the elements of the second and third groups are connected to the start input at structure.