SU1293844A1 - Device for transforming programs - Google Patents

Abstract

The invention relates to computing. Its use in digital information transmission systems expands the field of application. The device contains registers, key groups, an adder, a pulse distributor and a delay element. By introducing a register, groups of AND elements, a group of OR elements, a pulse generator, triggers, and an AND element, it is possible to convert codograms whose tetrads have different bases. I il. Yu

Description

The invention relates to computing and can be used in digital information transmission systems.

The purpose of the invention is to expand the field of application by transforming the codograms with a variable base of tetrads,

The drawing shows the functional diagram of the device.

A device for converting codograms contains the first 1, second 2 and third 3 registers, the first 4, the second 5 and the third 6 groups of keys, the adder 7, the distributor 8 pulses, n groups of 9 elements AND four in each group of 10 elements OR, generator 11 clock pulses, the first 12 and second 13 triggers, element 14, delay element 15. In the drawing, information inputs 16, inputs 17 and 18 Start and Stop, respectively, a group of 19 control inputs, outputs 20, and the pulse distributor 8 signals on outputs appear only from the second input pulse .

A device for converting codograms works as follows. ;

A transposable codogram is entered through inputs 16 in the form of a table, starting with the leading tetrad A. The Start command enters trigger II, and the clock pulses through AND 14 enters trigger 13. At the first clock, the information code written in a-tetrad arrives at adder 7. At the same clock cycle, keys 6 and the code values of the second register 2 (initially this goes to the third register 3. Since the control signal from inputs 19 to the register 3 does not arrive at the first clock of the device, the information from the register 3 does not enter into the adder 7. The value of the Code from the adder 7 is written to the register. On the second clock of the device va keys 5 are opened and the information code recorded in a tetrade from register 1 is rewritten into register 2, the sync pulse on the third cycle of the device operation, the information code recorded in the entered a notebook, enters through keys 4 into adder 7, register C through keys 2 6, the code of the previous a-tetrad enters the register 3. The discharge signal of the number written in register 3,

five

50

0

5 0 5 0 5

comes with a shift to the input of the adder 7, the shift is determined by feeding from the inputs 19 signals permitting the rewriting of the code recorded in the corresponding cells of register 3. The numbers of the cells of register 3 from which information is overwritten are determined by a binary number corresponding to the input base g tetrads. Thus, in the adder 7, the input tetrad and the previous one, which is increased as a result of the shift by a factor of g, are summed up. The result of the sum in register 1 is the binary code of the input number. On the fourth cycle of operation, the binary number from register 1 through the keys 5 is written to register 2. Then, at each odd device operation cycle, summation occurs in the adder 7 of the newly entered tetrad with the binary number recorded in register 2j increased in g. time. At each even clock cycle, the binary code from register 1 is fed into register 2,

Summation continues until the (2n + 1) th cycle of the device. At (2p + 1) -th cycle, the signal from switch 8 through the delay element 13 to the first cycle enters the input - Stop trigger 11, and the supply of clock pulses through the k-th element of the device stops. After the sync pulse on the (2p + + 2) cycle, the binary code of the number from register 1 is written to register 2 and counted at outputs 20, all registers must be cleared.

Thus, the device performs the conversion of variable base codograms of each tetrade (for example, J dec, hex, octal, etc.).

Claims (1)

Invention Formula A device for converting codograms containing the first group of keys, the outputs of which are connected to the first inputs of the corresponding bits of the mapper, the outputs of the bits of which are connected to the inputs of the corresponding bits of the first register, the outputs of the bits of which are connected to the first inputs of the corresponding keys of the second group, the outputs of which connected to the inputs of the corresponding bits of the second register, outputs the bits of which are connected to the first inputs of the corresponding keys of the third group, the pulse distributor and the delay element, the first inputs of the keys of the first group are information inputs of the device, the second inputs of the keys of each group are combined, in order to expand the application area by converting codograms with variable base tetrads in the device entered the third register, triggers, the element And, n groups of elements And, where n is the number of tetrads in the converted codogram, the group of elements OR, and clock pulse, the output of which and the output of the first trigger are connected to the inputs of the element I, the output of which is connected to the counting input of the second trigger, the direct output of which is connected to the input of the pulse distributor and the combined second input of the keys of the first and second groups, the inverse output of the second trigger is connected to combined second key entries ten 293844 The third group, the output of the i-ro key of which, where i 1, is connected to the information inputs of the bits of the third register from C4 (il) of the 13th to the 41st — whose outputs are connected to the inputs of the bits of the adder from (1 + 3) th outputs of the pulse distributor, except the last one, are connected to the first inputs of the elements AND of the corresponding groups, the output of the k-ro element I (, 2, 3,4) of the 1st group, where 1 (1, ..., n) is connected to The fth input of the k-ro element OR group, the output of which is connected to the control inputs A (k + ml)} - x 5 bits of the third register (, 1, ...), the last output of the pulse distributor through this the delay element is connected to the first input of the first trigger, the first input of which is the device Stop input, the second input of the first trigger is the device Start input, the second inputs of the elements AND of each group are corresponding to the control inputs of the device, the outputs of the second register are device outputs. 20 25 Editor E. Sligan Compiled by I. Bocharova Tehred V. Kadar Order 396/59 Circulation 902. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader T. Kolb