SU1302280A1 - Device for servicing requests - Google Patents

Abstract

The invention relates to computing, in particular, to devices for priority service of requests, and can be used in computer systems for processing data. The invention allows to expand the field of application of the device by organizing the priority of simultaneously received requests. The device contains 3N-1 groups of AND elements (N is the queue length), N storage and N-I intermediate registers, OR elements, priority block, control block. Requests arriving at the device are stored in the priority block in the order of their arrival from the 1st channel to the 0th (M is the number of request inputs of the device) and through the OR element, as trigger signals,. enter the control unit. The control unit generates the clock of the main sync series in the control circuit of the device, as a result of which requests are copied from the priority block. The device allows independent writing / reading of requests and assigning input / output of requests to the main sync series, 1 hp, f-ly, 3 sg. sl co about tsD BO 00 about

Description

The invention relates to the field of computing, in particular, devices for the priority service of requests, and can be used in multiprocessor computing systems for data processing,

The aim of the invention is to expand the scope by organizing the priority of simultaneously received requests,

Fig, 1 shows a structural diagram of the proposed device; Fig. 2 is the same, the control unit for L N 3, where M is the number of request inputs of the device, N is the length of the fixed request queue; FIG. 3 is a time diagram of the operation of the device.

The device contains memory. registers 1, intermediate registers 2, element groups AND 3-5, elements OR 6 and 7, request inputs 8-10, allowing outputs 11-13, priority block 14 consisting of M channels, and in each channel three triggers 15 - 17, the element is NOT J8, the four Elements AND 19-22, and from the second channel - an additional element AND 23, the control unit 24, containing the start 25 input, the read and store outputs 26 and 27, the clock input 28, the first input first groups of clock inputs 29, the first input of the second group of clock inputs 30, clock outputs 31 and 32, the second input of the first group of clock 33, the second, the input of the second group Clock inputs are 34, third inputs of the first and second groups of clock inputs are 35 and 36, respectively, clock outputs 37 and 38, buses 39 and 40 pointers Memory O, Memory 1 respectively, element 41, element 42, element group 43 , node 44 of the priority pulse selection, consisting of (N + 1) channels containing two triggers 45 and 46 each, three elements AND 47-49; the node 50 of the priority pulse selection consisting of N channels, and in each channel there are two triggers 51 and 52 and three I 53 elements

55.

The device works as follows.

Before starting work on a common shchina (not shown) reset the storage 1 and intermediate 2 registers, triggers 15-17 priority block 14 and triggers 45,46,51 and 52 nodes 44

and 50 priority selection of pulses of control unit 24, respectively, of each channel, a reset pulse is received and sets them to the initial zero state.

An end-to-end transfer circuit is formed (if not a single request pulse is received at inputs 8-10) of synchronization pulses from clock input 28 through AND 42 to clock output 38.

Let, at the moment of time t (fig. 3), the inputs 8-10 of each of the M channels simultaneously received requests and fixed in the trigger 16 of their channel, in a pause (before the synchronization pulse), through the element 22 of each channel, the request is written to the trigger 17, A single trigger output 17 of the first channel prepares the AND element of the first channel of the AND group 5 for opening, and the zero output of the trigger 17 blocks AND elements 23 of the subsequent channels of the priority block 14.

The high level of the signal from the single output of the trigger 16 of each of the M channels goes to the inputs of the OR element, from whose output to the 25 start input of the control unit 24 that is connected to the first inputs of the elements AND of the element group AND 43, at the second input of the element And of the group of elements And 43 there is a single signal level from the zero output of the trigger 51 of the node 50 of the priority pulse selection, and the subsequent elements AND groups of elements And 43 are blocked by zero signal levels coming from the single outputs of the trigger 52 of the node 50 priority th pulse selection of previous channels,

Trigger 45 of the first channel is set to one state in the pause (before the synchronization pulse) And this channel element 48 will set the trigger 46 to one state. The latter prepares for opening the element And 49 of its channel and blocks the element And 49 of the subsequent channels and the element And 42,

Next, the first synchronization pulse is output to output 30, zero input of the trigger 45 of node 44 of the priority pulse selection, single input of the trigger 51 of node 50 of the priority selection of pulses of the N-ro channel and to one of the inputs of the OR 6 element,

A positive pulse arriving from output 30 to the first inputs of the N-OI group of elements AND 5 selected from the synchronization series records the first request received at input 8 of the device to the N-th storage register 1, the trigger 45 of the priority selection node 44 is set. pulses to the initial zero state and setting the trigger 51 of the N-ro channel of node 50 of the priority selection of pulses to one state,

The impulse from the output of the element OR 6, through the element AND 20 of the first channel of the block 14 priority, sets the one state of the trigger 16, and the trigger 15 to the initial zero state (the low level of the signal from the zero output. The trigger 15 blocks the action of the request signal by input 8, if its duration is more than one period of the synchronization frequency).

In the pause (after the synchronization pulse), the trigger 17 of the first channel of the priority block 14 returns to its initial state, blocking the AND element of the first channel of the And 5 elements, and prepares the And element for the subsequent 23 channels for opening. In addition, the trigger 52 of the node is set to pause 50 priority selection of impulses of the N-ro channel into a single state, which prepares the next element And the group of elements And 43 for opening,

Trigger 45 of the second channel is set to one state and paused (before the synchronization pulse through element 48 of this channel, the trigger 46 is set to single, then the second synchronization pulse is selected at output 34, the request entry received at input 9 is written to (NI) memory register 1 and, similarly to that considered (works of the 1st channel) resetting the 2nd channel of the priority block 14 and the priority pulse selection node 44 to the initial state.

Similarly, it occurs for filling from (N-l) -ro of the storage register 1 to the 1st storage register 1,

When filling N storage registers 1 devices on the bus pointer

Memory 1 appears at a single signal level, and at clock output 38 a synchronizing series that differs from the previous one (input 28) by the absence of pulses selected at outputs 3.34 and 36, i.e. corresponding to the number of requests received during this time at the inputs of 8-10 devices.

Further, some real device is processed (reading incoming requests, for this the real device exposes a single signal level to the input 27 of the device.

For ease of perception of the reading mode, consider the operation of the proposed device in the autogenerator mode. To do this, mentally connect the control outputs 26 and 27 with the inputs 39 and 40 of the device. Accordingly,

When a pulse device appears at output 36, the first channel 51 of the first channel of the node 50 of the priority pulse selection is set to one, which will result in the trigger 45 of the channel of the priority pulse selection of the single channel 44, which will be paused installation of the trigger 46 (N + 1) channel in one state, and the first pulse of the negative phase of the synchronization series from output 32 of the information contained in (NI) storage registers 1, is rewritten through the corresponding groups of elements And 3 in the space daily registers 2 devices.

The positive phase pulse of the synchronization series from the output of the element And 49 (N + I) of the node channel 44 priority, the pulse selection is fed to the interrogation inputs of the device elements And 5 and the interrogation inputs of the elements 55 of the node 5 priority pulse selection of each of the N channels , census from intermediate registers 2 to memory registers takes place

1 requests received, 1

The impulse from the output of the 35-node 50 of the priority selection of pulses of the first channel arrives at the zero input M of the flip-flops of the 1st reg signal of register 1 and sets it to the initial zero state. The same pulse arrives at the zero input of the trigger 51 of the 1st channel of the node 50 of the priority pulse selection and sets

its in the initial zero state, which blocks the element And 54 and prepares the element And 53 of this channel for opening. In the next pause, there is an intermediate shift of information by another intermediate shift of the node 50 of the priority pulse selection to the initial zero state,

. The next pulse of the positive phase of the synchronization series (output 33) performs the final shift of information by one more storage register 1 and reset to the initial zero state of the next storage - register,

Memory registers 1 of the device are freed from the 1st channel to the Nth,

At the time of processing (reading), the next request is received on any of the request inputs 8-10, then the pause will be set to one state of the trigger 45 of the nearest vacant channel (i-ro channel)

A series that differs from the previous (input) by the absence of pulses is equal to twice the number of incoming requests on the inputs 8-10 of the device.

Claims (2)

1. A device for servicing requests containing N storage registers (N. is the length of the service queue), (N-I) intermediate registers, groups of elements AND, of which (2N-1) groups of elements And contain 2M elements AND (M is the number of request inputs of the device) and N groups of M elements I in each, with the direct and inverse outputs of the i-th memory register (i 1, 2 ..., N-1) are connected to the first inputs of elements AND of the i-th group, the outputs of which are connected to the direct and inverse inputs of the i-th thirty 35 40 her requests, two OR elements are entered into it, the control block and the priority block containing M channels, in each f-m channel (f 1, M) are triggers, the element is NOT and  four elements And, and in the q-th channel (q 2, M) - the additional fifth element And, we take the f-th request device input connected to the first input of the first element And f-ro channel of the block .jQ priority and the input element is NOT the f-ro channel of the priority block, the output of which is connected to the zero input of the first trigger of the f-ro channel of the priority block, the zero output of which is connected to the second input of the first element AND the f-ro channel of the priority block whose output is connected with a single input of the second flip-flop f-ro channel of the priority block, the single and zero outputs of which are connected to the first inputs of the second third elements And the f-ro channel of the priority block, respectively, whose outputs are connected to the single and zero inputs respectively the third flip-flop f-ro channel of the priority block, the single output of the third flip-flop q-ro channel of the priority block is connected to the first input of the fourth element AND the q-ro channel of the priority block, the zero output of the third flip-flop of the priority block channel (L 1, M-1) is connected to the (L + 1) th input of the fourth element of the AND (L + 1) -th channel of the priority block, the unit output of the third trigger of the first channel of the priority block and the outputs of the fourth element f5 the unit output of the second flip-flop of each channel is connected to the second input of the third element AND of the corresponding channel, the zero output of the second flip-flop d-ro channel (, N) is connected to And the q-ro channel of the priority block is connected to the first inputs of the corresponding 20th inputs (c 3, N + 3) of the third element And the 1st group and the first And (d + l) -ro channel, the outputs of the third The element And d-ro channel of the first pulse selection node are the second group of clock outputs of the control unit and are connected to the zero input of the first flip-flop d channel, the clock input of the control unit is connected to the first input of the third element And of each channel of the first node c. the inputs of the fifth elements AND the f-ro channel of the Priority block, the second inputs of which are connected to the output of the first element OR, the single input of the first trigger and the zero input of the second trigger of the f-ro channel of the priority block o connected to the output of the pth element 25 And the f-ro channel of the priority block, the first clock output of the control block is connected to the second inputs of the second and third elements of all channels of the priority block, the single outputs of the second trigger of all channels of the block lectures of pulses, the first input of the element AND, the input of the element NOT, the output of which is connected to the second inputs of the first and second elements AND of each channel, each of the priority nodes are connected to the group of inputs 35 of the pulse lecture and is the first The second OR element, the output of which is connected to the start input of the control unit, the output of the NOT element f-ro channel of the priority block is connected to the zero input of the first flip-flop channel of the priority block, the first group of clock outputs of the control unit is connected to the second inputs of each i-ro storage register , the second inputs of elements AND 8 of the group are connected to the i-th output of the second group of clock outputs of the control unit and to the group of inputs of the first element OR, the second inputs of elements AND of the i-th group are connected to the second clock output of the control unit , The second inputs of the AND K th group are connected to a third clock output control unit, the clock input device is connected to the clock input of the control unit, 2, The device according to claim 1, 1, and TL is that the control unit contains the element NOT, the element AND, the group of elements AND, two pulse selection nodes consisting of (N + I) and N channels, respectively but in each channel of each node of the priority pulse selection, there are two triggers and three AND elements, with zero and single outputs of the first trigger of each channel of each selection node o pulses are connected to the first inputs of the first and second elements of the channel, respectively, the outputs of which are connected respectively to zero single inputs of the second channel trigger, 5 a single output of the second trigger of each channel is connected to the second input of the third element AND of the corresponding channel; the zero output of the second trigger of the d-ro channel (, N) is connected to The 0 inputs (c 3, N + 3) of the third element And the (d + l) -ro channel, the outputs of the third element And the d-ro channel of the first pulse selection node are the second group of clock outputs of the control unit and are connected to zero the input of the first trigger of the d-ro channel, the clock input of the control unit is connected to the first input of the third element AND of each channel of the first node se- 20 30 25 inputs (c 3, N + 3) of the third element And the (d + l) -ro channel, the outputs of the third element And the d-ro channel of the first pulse selection node are the second group of clock outputs of the control unit and are connected to the zero input the first trigger of the d-ro channel, the clock input of the control unit is connected to the first input of the third element AND of each channel of the first node of the lectures of pulses, the first input of the element I, the input of the element NOT, the output of which is connected to the second inputs of the first and second elements AND, each of the channels, each of the nodes is set by the output output of the control unit, the single input of the first trigger d-ro of the first pulse selection node connected to the output of the d-ro element And the groups of elements And, and the zero and single inputs of the first trigger (N + l) -ro of the channel of the first pulse selection node are the inputs for reading and storing device requests respectively, the outputs of the second and third elements AND (N + l) -ro of the channel of the first pulse selection node are the second and third clock outputs of the control unit, respectively, the output of the third element of the AND (N + l) -ro channel of the first pulse selection node is connected to the first the inputs of the third element And the d-ro channel of the second node of the selection of pulses, the outputs of the third element And the d-ro channel of the first node of the selection of pulses are connected to the single inputs of the first triggers of the d-ro channel of the second 91 pulse selection node, zero output of the first d-ro trigger of the channel of the second pulse selection node is connected to the first input of the d-ro element AND of the And group of elements, the single output of the second trigger of the h-ro channel (h a 2, N) of the second pulse selection node is connected to the second input of the h-ro element And the group of elements of Ls, the third inputs of the elements AND of the group are connected to the start input of the control unit, the zero output of the first trigger of the N-ro channel and the single output of the first ten the trigger of the first channel of the second pulse selection node are outputs of the pointers Memory O and Memory 1, the inputs of the AND element are connected to the zero output of the second trigger of each channel of the first node of the priority pulse selection and clock. the input of the control unit, vi) the stroke is the output of the interface of the device, the outputs of the third element And the d-ro channel of the second node are the first group of clock outputs of the control unit. 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