SU955067A1 - Data channel polling device - Google Patents

Description

(54) DEVICE FOR INFORMATION CHANNEL POLL

one

The invention relates to telemechanics and computing technology and is intended for use in software polling devices of information channels with automatic selection of the polling order.

A device for polling information channels is known, comprising frame and scanning counters, an analysis unit, a command register, a memory device, a decoder, an adder, and an operational register 1.

The disadvantage of this device is the requirement that the addresses of the memory cells in which the codes of the polling frequencies of the channels with the numbers of these channels are written coincide, which limits the possibility of operative intervention in the process of the device operation.

The closest to the proposed device is a device for interrogating telemetry channels, containing a series-connected counter, a memory, an analysis unit, a multiplexer, two registers, a key block, an And element, a trigger, two adders, a second memory device, and a clock and input bus 2.

A disadvantage of the known device is the hard dependence of the polling frequency.

any of the channels from higher polling frequencies, which narrows the base set of frequencies and makes it difficult to quickly change the sequence and frequency of polling channels during operation of the device.

The purpose of the invention is to expand the scope of the device.

Claims (2)

The goal is achieved by the fact that the device for polling information channels containing two memory blocks, a counter, two registers, the first And element, two adders and the first block of And elements, the output of the first And element connected to the clock input of the counter, the output of which is connected with the first address input of the first memory block, the first output of the first register is connected to the first input of the first adder, the first input of the first element I is the clock input of the device, two elements are NOT, the second element is AND, the third and fourth p the second and third blocks of the And elements, the third adder, three comparison circuits and the delay element, the output of the first And element connected to the clock inputs of the first memory block, the first and second registers, and through the delay element to the read input of the first memory block and the first input of the second element And, the output of which is connected to the clock inputs of the second memory block, and the third register and the first input of the first block of elements And, the second input of which is connected to the Output of the third register, the input of which is connected to the output of the second A memory unit, the first address input of which is connected to the output of the second register, the input of which is connected to the output of the first adder, the second input of which is connected to the second output of the first register, the first input of the first comparison circuit and the first input of the second adder, the second input of which is connected to the second the input of the second element AND and the output of the first element NOT, the input of which is connected to the output of the second comparison circuit and the first input of the second block of elements AND, the first address input of the device is connected to the second address input of the second of the first memory input, the information inputs of the first memory block are connected respectively to the first, third and fourth outputs of the first register, the outputs of the second and third blocks of the And elements and the second information input of the device, the second input of the second block elements And is connected to the output of the third adder, the first input of which is connected to the fifth output of the first register and the first input of the second comparison circuit, the second input of which is connected to the third output oh the first register and through the second element NOT to the third input of the second element I and the second input of the third adder, the counting input of the counter is the interrogation input of the device, the output of the counter is connected to the first input of the third comparison circuit, the second input of which is connected to the output of the fourth register the input of which is the recording entry of the device, the output of the third comparison circuit is connected to the second input of the first element I, the second address input of the first memory block is the second address input of the device, the first and Ora third inputs of the AND unit connected respectively to the outputs of the second adder and the first comparison circuit. The drawing shows a block diagram of a device for polling information channels. The device contains a counter 1, memory block 2, adder 3, register 4, memory block 5, registers 6-8, comparison circuits 9-11, elements NOT 12 and 13, delay element 14, elements 15 and 16, adders 17 and 18, And 19-21 blocks of elements, address inputs 22 and 23, information inputs 24 and 25, clock input 26, recording input 27 and interrogation 28 device input. The proposed device works as follows. The device polls the information channels from any of the frequencies an integer number of times lower than the basic polling frequency. The frequency of polling of each channel does not depend on the number of this channel, nor on the frequency of polling other channels and can be quickly changed during operation of the device. Before starting work (if necessary and during operation), the number of the channel to be interrogated at the address from input 23 (addressing starts at zero cell) is written to input 25 at each input 25, with the numbers of channels polled with the same frequency cc in successive cells, i.e., grouped. The information on one of the channel groups (starting from the first cell) polled with the same frequency is recorded in each of the cells of the memory 2 at the input 24. Each cell of the storage device 2 is conventionally divided into five groups of several bits E each. The group of lower bits is used to organize the polling channel counter (zeroes are recorded in the initial state), the next group records the number one less than the number of channels polled at this frequency, the next bit group is assigned to the polling counter organization (the initial state is zero), then the number is written, one less than the division factor of the basic sampling frequency nj, and the address of the group of channels polled with this frequency is entered in the higher bits. Register 6 records a number that is one greater than the number of groups of channels w polled at the same frequency. The input 26 receives a clock frequency that is m or more times higher than the base sampling frequency. The interrogation pulse at input 28 sets the counter 1 to the zero state, as a result of which the output of the comparison circuit 11 is set to allow the clock to pass through the AND 15 element to the input of the counter I. During the period between the interrogation pulses, the clock pulses alternately select information from block 2 channel groups used to determine the channel numbers to be polled at a given time interval. Clock pulses arrive at the counting input of counter 1 working on the leading edge, thereby setting the addresses of the cells to be sampled from block 2. The leading edge of each clock pulse reads the contents of the next cell of block 2 and writes them to the register 7. In the adder 3 they are summed initial channel group adress, polled with the same frequency, with the polled channel counter value (the initial state of the counter is zero). The cell address with the polled channel number generated in this way is written into the register 4 by the leading edge of the clock pulse, and from there it goes to the address input of the cell 5. The read resolution signal is generated at the output of the comparison circuit 9. If the value of the opro counter (the third output of register 7) differs by more than one from the division factor of the basic sampling frequency (does not coincide with the fourth output of register 7), then the output of the comparison circuit 9 is set to level "1 allowing the passage through block 19 unchanged or increased per unit in the adder 17, the poll counter value for further rewriting it into the corresponding bits of the cell 2. Block overwriting the poll counter value without changes occurs when this channel group is to be sued yuchena of polling, t. e. in all its bit rows recorded values "1, which causes the appearance at the output of NOT element 13, prohibiting layer" O. Thus, after the arrival of the n polling pulses, the output of the circuit 9 is set to "O. In this case, the output element NO 12 is set to allow the clock pulse delayed by the delay element 15 to pass through the element 16. This pulse reads the back edge of the polled channel number 5, writes it to the register 8, and enables the channel 31 to interrogate. At the same time, the output of block 19 is set to zero, i.e., the polling counter is reset to the initial state, and preparations are made to sample the contents of the next cell of block 5, i.e., to poll the next channel for polling through the nj. For this, the counter value of the polled channels in the adder 18 is incremented by one. The comparison circuit 10 determines whether all channels of a given group are polled. If not, a potential is established at its output, allowing the passage through block 20 of a new value of the polled channel counter to one of the inputs of block 2 with a view to further rewriting it into the corresponding bits of the cell. Otherwise, the signal from the output of circuit 10 sets a zero level at the output of block 20, thereby bringing the polled channel counter to the initial state in order to start polling the channels of this group again. The values of the second, fourth and fifth, as well as the modified values of the first and third groups of bits of the register 7 are recorded by the falling edge of the delayed clock pulse in cell of block 2. With the arrival of the next clock pulse, the value of counter 1 is increased by one, the contents of the next cell of cell 2 are sampled and all subsequent operations. This process occurs until the value of counter 1 does not coincide with the contents of register 6, i.e., all the cells of block 2 are not read. In this case, the signal from the output of circuit 11 blocks the passage of clock pulses through AND 15. The next polling pulse sets counter 1 is reset and the whole process is repeated. Thus, during the time between the two polling pulses, all cells of block 2 are alternately analyzed and the necessary channels are polled. If it becomes necessary to change the polling order of channels, their numbers or polling frequencies (as determined by external devices), this is easily accomplished by correcting the source data in blocks 2 and 5 and register 7 for inputs 22-25 and 27. Thus, the proposed the device allows polling channels with automatic tuning to any independent polling frequencies and it is easy to change the polling modes during operation of the device, which allows it to find wide application in telemetry and computing systems. The invention The device for polling information channels containing two memory blocks, a counter, two registers, the first And element, two adders and the first block of And elements, the output of the first And element connected to a clock input of the counter, whose input is connected to the first the address input of the first memory block; the first output of the first register is connected to the first input of the first adder; the first input of the first element I is a clock input of the device, characterized in that, in order to expand the scope, it contains two elec NOT, the second element And, the third and fourth registers, the second and third blocks of the elements And, the third adder, three comparison circuits and the delay element, the output of the first element And connected to the clock inputs of the first memory block, the first and second registers and through the element delays with the read input of the first memory block and the first input of the second element I, the output of which is connected to the clock inputs of the second memory block and the third register and the first input of the first block of elements AND, the second input of which is connected to the output of the third re istra, whose input is connected to the output of the second memory block, the first address input coupled to an output of the second register having an input connected to the output of the first adder. the second input of which is connected to the second output of the first register, the first input of the first comparison circuit and the first input of the second adder, the second input of which is connected to the second input of the second element AND and the output of the first element NOT whose input is connected to the output of the second comparison circuit and the first input of the second And, the first address input of the device is connected to the second address input of the second memory block, whose information input is the first information input of the device, the information inputs of the first block n The cells are connected respectively to the first, third and fourth outputs of the first register, the outputs of the second and third blocks of the And elements and the second information input of the device, the second input of the second block of And elements connected to the output of the third adder, the first input of which is connected to the fifth output of the first register and the first input of the second comparison circuit, the second input of which is connected to the third output of the first register and through the second element NOT to the third input of the second element AND and the second input of the third adder, the counting input account The key is the interrogation input of the device, the counter output is connected to the first input of the third comparison circuit. the second input of which is connected to the output of the fourth register, whose information input is the recording entry of the device, the output of the third comparison circuit is connected to the second input of the first element AND, the second address input of the first memory block is the second address input of the device, the first and second inputs of the third block of elements And they are connected respectively to the outputs of the second adder and the first comparison circuit. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 720720, cl. H 03 K 17/02, 1980. 2. USSR author's certificate jvb 705678, cl. H 03 K 17/02, 1979 (prototype).