SU1168969A1 - Analyser of durations of random process spikes - Google Patents

Abstract

ANALYZER prolonged release STOCHASTIC PROCESSES comprising counter threshold element, first and second inputs of which are respectively data input and specifying the analyzer layer and the output of the threshold element is connected to a first input of AND gate and input of the pulse shaper, a first output coupled to an input of OR whose second input is connected to the output of the first delay unit, whose input is combined with the input of the interval counter and connected to the output of the last bit of the shift register The information input input is connected to the output of the OR element, and the control input is connected to the output of the AND element, the second input of which is connected to the output of the pulse generator, the output of the interval counter is connected to the address inputs of the memory elements, the write control inputs - which are combined and connected to the output of the second delay unit, the input of which is connected to the second output of the pulse generator, characterized in that, in order to simplify the analyzer, the second delay unit consists of two series-connected elec (Delays, the output of the first of which is connected to the counter input of the counter, the recording resolution input of which is connected to the second output of the pulse former, and the information input of the counter is connected to the combined memory element outputs, outputs o: the sampling permissions of which are connected respectively to the bit besides the output of the last bit, the shift register, and the information inputs of the memory elements are combined and connected to the output of the counter.

Description

The invention relates to automation and computing and can be used to quickly determine the density distribution of the durations of emissions of random processes.

The purpose of the invention is to simplify the analyzer of the duration of emissions of random processes.

FIG. 1 shows the structure of the proposed analyzer in FIG. 2 - plots showing his work.

The analyzer contains memory elements 1, the address inputs of which are combined and connected to the output of counter 2 intervals, counter 3 and threshold element 4, whose inputs are the corresponding inputs of the analyzer, and the output connected to the input of the pulse shaper 5 and one of the inputs of the AND element 6. Another input element AND 6 is connected to the output of the generator 7 pulses, and the output is connected to the control input of the shift register 8, whose information input is connected to the output of the element OR 9. The last bit output of the shift register 8 is connected to the input m counter 2 intervals and the input of the first block .10 delay, the output of which is connected to one of the inputs of the elements OR 9, the other input of which is connected to one output of the driver 5 pulses, the other output of the driver 5 pulses connected to the input of the second block 11. delayed input the delay element 12, the output of which is connected to the counting input of the counter 3 and the input of the element 13 for the holder. The output of the delay element 13, which is the output of the second delay unit 11, is connected to the combined inputs of the recording control - the counting of the memory elements 1. One of the outputs of the driver 5 pulses is connected to the input of the record of the counter 3. The bit outputs of the memory elements 1 are combined and connected to c; the information inputs of the counter 3, whose outputs are connected to the combined information inputs of the memory elements 1, the sampling resolution inputs of which are connected to the corresponding bit outputs of the shift register 8.

The analyzer works as follows.

In the initial state, in all cells of the memory elements 1, in all bits of the shift register 8 and the 2 interval intervals, zeros are written. In the block diagram, the circuits ensuring the initial state of elements 1, 2, and 8 are not shown, because they are well known, and their image complicates the scheme. The random process X (t) under study enters the input of threshold element 4, to the second input of which a voltage U is applied. corresponding to the level of analysis. When a random process X (t) is emitted exceeding the level of analysis U ,. at the output of the threshold element 4, a rectangular impulse, is formed, the duration of which is equal to the duration of the ejection (Fig. 2b). The pulses from the output of the threshold element 4 arrive at the input of the element 6 and are filled with the pulses of the generator 7 of pulses. At the leading edge of the pulse duration cg, at the first output of the pulse generator 5, a pulse appears (Fig. 2c) which, after passing through the OR 9 element, writes a unit to the first digit of the shift register 8. The pulses from the output of the element 6 enter the control input of the shift register 9 and shift the unit to the right. If the duration of the surge 1 (where ut. Is the pulse period of the generator 7 pulses, 1 is the number of bits of the shift register 8), then the pulse corresponding to the end of the surge, from the second output of the pulse generator 5 pulses (Fig. Zg), enters the recording input the counter 3, records in it information arriving at its information inputs from the output of the i-ro memory element 1, and the address (number) of the cell from which information is being read is determined by the state of the counter 2 intervals. The same pulse from the second output of the imaging unit 5 pulses (Fig. 2d), having passed through the delay element 12, enters the counting input of the count 3 and adds 3 to the contents of the counter. Then, after a time interval determined by the delay element 13, a signal appears at the output of this element, recording information from the output of counter 3 into the same memory element 1 and into the same memory cell from which the information was recorded counter 3. At the same time, the memory element from which information is recorded in counter 3 and in which new information is recorded from counter 3 is determined by the state of the shift register 8 and selected using the signal from the i-ro output of the shift register 8 (i 1 , 2, .. ,, 1) entering the sample resolution input i-ro of memory element 1. If j} g5ut 1, then the unit shifts to the last bit output of the shift register 8 and at the falling edge of the signal from the last bit output of the shift register 8, one is added to the contents of the interval 2 counter, and after the time interval defined by the first delay block 10 , the pulse from the output of the first block 10 of the delay through the element OR 9 passes to the information input of the shift register 8, carried out a second recording of the unit for the first digit. Then the snobs from the output of the element AND 6 unit from the first digit of the shift register 8 move to the right and, if Q 2 it -I, one again adds to the contents of the 2 interval counter, and the interval determined by the first block 10 for the delay, the unit will be written for the first digit of the 8 shift register. This process occurs until the release of the random process X (t) is completed. At the trailing edge of the pulse Sc, a pulse is formed at the second output of the pulse generator 5 (Fig. 2d 9) writes information 3 to the counter from the output of the i-th memory element 1, the address of the memory cell from which the information is read; state of the interval 2 interval.After that, the unit from the output of the delay element 12 is approached by the cn ala, and the signal from the delay element 13 records information from the output of the counter 3 into the memory cell of the i-ro memory element 1, condition The interval counter 2 and the shift register 8 are set to the initial state of the initial state setting (not shown) by the arrival of each new pulse Ce of the shift register 8 and the interval counter 2 in the corresponding cells of memory 1. information is accumulated, which is necessary for constructing a histogram of the values of the duration of the emissions of the random process X (t) under study. Statistical estimate of the probability density of the durations of the emissions W, -: in each interval, the duration ut is determined by the formula D m the content of the j-th memory cell (, 2, ..., 1) of the i-ro memory element 1 - j 1,2, ... k.

2

Claims (1)

ANALYZER OF DURATION EMISSIONS 'RANDOM PROCESSES, containing a counter, a threshold element, the first and second inputs of which are respectively the information input and the input of the level analyzer and the output of the threshold element is connected to the first input of the element And and the input of the pulse shaper, the first output of which is connected to the first input of the element OR, the second input of which is connected to the output of the first delay block, the input of which is combined with the input of the interval counter and connected to the output of the last bit of the shift register ha, the information input of which is connected to the output of the OR element, and the control input is connected to the output of the And element, the second input of which is connected to the output of the pulse generator, the output of the interval counter is connected to the address inputs of memory elements, the write control inputs - by reading which are combined and connected to the output the second delay unit, the input of which is connected to the second output of the pulse shaper, characterized in that, in order to simplify the analyzer, the second delay unit consists of two series-connected elements costs, the output of the first of which is connected to the counting input of the counter, the recording permission input of which is connected to the second output of the pulse shaper, and the information input of the counter is connected to the combined outputs of the memory elements, the sampling resolution outputs of which are connected respectively to the discharge outputs, except for the output of the last bit, register shift, and the information inputs of the memory elements are combined and connected to the output of the counter. SU, 1168969