SU1527660A1 - Device for digital magnetic recording - Google Patents

Abstract

The invention relates to the accumulation of information and can be used for digital magnetic recording. The purpose of the invention is to increase the density of a digital magnetic recording. Upon receipt of clock pulses from the master oscillator 1 to the trigger 13, the matrix row of the first memory block 12 specified by the code combination on the first group of outputs of the static register 7 is polled. The latter causes the matrix rows of the second memory block 12 to be interrogated by the code combination on the second group of outputs of the static register 7, etc. Due to this, a complete code appears at the outputs of memory block 8, the combinations of which are randomly arranged. Block 8 of memory through the element OR 14 opens the element AND 4, which ensures the recording of a new combination from the first group of outputs of the static register 7 to the static register 10, acting on the block 11 of the record. 1 il.

Description

The invention relates to the accumulation of information, namely, devices for digital magnetic recording.

The aim of the invention is to increase the density of a digital magnetic recording.

The drawing shows a device for digital map recording.

The device contains a master generator 1 connected by an output to the first input of the first element AND 2, an input of the delay element 3 and the first input of the second element 4 connected to the first input of the trigger 5, the first memory block 6 connected by the outputs to the first group - only the inputs of the first static register 7, the second memory block 8, the comparison block 9, the second static register

10 and a recording unit 11 made in the form of a magnetic recording apparatus. At the same time, the second memory block 8 is connected by the first group of address inputs to the last group of outputs of the first static register 7 and connected to the first group of information inputs of the comparison block 9 by the outputs.

The device also contains additional memory blocks 12 connected by outputs to the remaining groups of information inputs of the first static register 7, additional trigger 13 connected by a counting input to the output of delay element 3 and connected by an output to the address input of the first memory block 6, and OR 14. Element OR 14 is connected by an output to the second input of the second element AND 4 and is connected by inputs to the outputs of the first memory block 6 connected to its group of address inputs. Additional memory blocks 12 are connected by the first groups of address inputs to the remaining groups of outputs of the first static register 7, the first of which is connected to the information inputs of the second static register 10 connected by outputs to the inputs of the block

11 records and connected by a synchronization input to the output of the second element 4, Outputs of the first memory block 6 are connected to the second group of address inputs of the first of the additional memory blocks 12, each of which is connected to the outputs of the second group of address inputs of the subsequent additional memory block 12 The last of which is connected by outputs to the second group of address inputs of the second memory block 8. At the same time, the output of the trigger 5 is connected to the second input of the first element I 2 connected by the output to the control input of the comparison unit 9, which is connected by the second group of information inputs to the input buses 15 of the digital information and connected to the clock input of the first static register 7 and the second trigger input five,

The digital magnetic recorder works as follows (after the

Clock pulses from master oscillator 1 are fed continuously through delay element 3 to the counting input of an additional trigger 13, affecting the first memory block 6 in the first memory block 6, in the first memory block 6, a two-row matrix of code combinations is located that corresponds to the calculation rule, According to which the code combination must find a place in each of the columns of the matrix, its value is equal to the corresponding column address. At the same time, the rest of the vacant positions of the matrix columns contain code combinations that are larger by one than the addresses of the corresponding columns. Due to this, the additional trigger 13 and the first memory block 6 work as a binary counter. In the additional memory blocks 12 and the second memory block 8, different combinations of matrices of matrices should be placed, corresponding to the structure of the Latin square rule, according to which the compliance of all code combinations of each row and column of the matrix to the full code is regulated. code combinations The addresses of the row and column of the memory cell in the matrix from which the code combination is read are set, respectively, on the first and second groups of address inputs memory blocks 12 and the second memory block 8.

Upon receipt of the clock pulses on the additional trigger 13, the matrix of the first additional memory block 12 is sequentially polled, which is set by the code combination on the first group of outputs of the first static register 7.

The second additional memory block 12 is specified by a code combination on the second group of outputs of the first static register 7 ,. etc. Thanks to this at the outputs of the second block

8, a full code appears, the combinations of which are arranged in random and random order. At a certain value of the code combination at the outputs of the second memory block 8, the OR 14 element forms a logical unit level ensuring the opening of the second element AND 4. At the same time, the next clock pulse from the master oscillator I passes through the second element 4, ensuring the recording of a new combination with the first group of outputs of the first static register 7 to the second static register 10 and set the trigger 5 to the state allowing clock pulses through the first element 2 to the control input of the block

9 comparison. If, after the arrival of several clock pulses, the first and second groups of information inputs of the comparison block 9 turn out to have equal code combinations, then a pulse equal in duration to the clock pulse is formed at its output. This pulse returns the trigger 5 to the initial state, prohibiting the passage through the first element AND 2 clock pulses to the comparison block 9, and updates the contents of the first static register 7. At the same time, the code combinations from the outputs of the additional memory blocks 12 and the second memory block 8 These are rewritten into the first static register 7, erased

it contains the same information.

Upon receipt of the clock pulses from the master oscillator 1, an additional trigger 13 and the first memory block 6 calculate them, which ends when a zero combination appears at the outputs of the second memory block 8. When this occurs, the formation of the signal overwriting information from the first static register 7 to the second static register 10, which affects the block 11 of the recording, providing a record on the magnetic recording media.

The use of the invention by transcoding the recorded information allows a considerable degree

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nor increase the density of digital magnetic recording.

Claims (1)

Invention Formula A device for digital magnetic recording containing a master oscillator connected by an output to the first input of the first element I, to the input of a delay element and to the first input of the second element I connected to the first input of a trigger, the first memory block connected by outputs to the first group of information inputs the first static register, the second memory block connected to the first group of address inputs to the output group of the first static register and connected to the first group of information inputs of the block A second static register, a recording unit, and digital information input buses, characterized in that, in order to increase the density of digital magnetic recording, an additional trigger is inserted into it, connected by a counting input to the output of the delay element and connected to the output address of the first memory block , element Я1Й, connected to the input to the second input of the second element, And, i connected by inputs to the outputs of the first memory block, connected to its group of address inputs, and additional memory blocks, connected to the outputs and to the remaining groups of information inputs of the first static register and connected by the first groups of address inputs to the remaining groups of outputs of the first static register, the first of which is connected to the information inputs of the second static register connected by outputs to the inputs of the recording unit and connected by a synchronizing input to the output of the second element And, and the trigger output is connected to the second input of the first element I, connected by an output with an upstream input of the comparison unit, which is connected to swarm group of information inputs to the input digital data buses and the output connected to the clock input of the first register and static to the second input flip-flop, and outputs a first block memory connected to the second group of address inputs of the first additional memory blocks, each of ko0 five five  15276608 These are connected to the outputs from the second: - the corpse of which is connected to the output of the address inputs of the next to the second group of address inputs of the secondary memory block, the last memory block.