SU1287254A1 - Programmable pulse generator - Google Patents

Abstract

The invention relates to a pulse technique. Designed for the formation of a series of rectangular voltage pulses with arbitrary time parameters. It can be used, for example, as a generator of control pulses in radio spectroscopy. The aim of the invention is to expand the range of durations generated by the pulse generator. To achieve this goal, delay blocks 17, 18 are introduced into the device, new functional connections are formed. In addition, the device contains a control block 1, a generator of 16 clock pulses, an operational memory (RAM) 13, an interval length counter 15, a register 14. A block 18 consists of registers 19, a counter 20, switches 21. The description of the invention shows execution of block 1. 2 3.p. f-ly. 1 il. ABOUT)

Description

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The invention relates to a pulse technique, is intended to form a series of rectangular voltage pulses with arbitrary time parameters and can be used, for example, as a generator of control pulses in radio spectroscopy.

The purpose of the invention is to expand the range of durations generated by the pulse generator.

The drawing shows the functional diagram of the programmable pulse generator.

The programmable pulse generator contains a control unit 1 consisting of a remote control 2, a pulse counter 3, elements 4 and 5, an AND-6 element, a BAN 7 element, 2I-OR 8 elements, 9-P flip-flops, a repeater block 12, an operational memory (RAM) 13, register 14, interval duration counter 15, clock generator 16, first delay unit 17, second delay unit 18 consisting of registers 19, counter 20 and switch 21, with data outputs block

When fed from console 2 to the bus. Potential zero logic mode, the programming mode is implemented. In this case, the register 14 ,. and with the help of the element IS-NE 6 the delay block 17 and the trigger 11 of block 1 are reset to the initial state. At the outputs of the counter 3 and at the inputs of the data Hbix RAM 13 are set the potentials specified from the console 2 defining the address of the RAM cell 13 and the code that by giving a logical unit from the console 2 triggers 9 and 10 and element 2I-OR 8 produce a pulse coming through the element BAN 7 on

1 control is connected to information-30 p ,, it is necessary to write into the cell, the operational inputs of RAM 13, whose address inputs are connected to the address outputs of control unit I, the start output of which is connected to the first input of delay unit 18, the first and second „„, „

,,, S is the input of RAM 13 and the recording permission of the control outputs of the unit 1 connection. information to the appropriate cell dinene with the first and second controls i-

The inputs of the RAM 13, the third control output of the unit 1 is connected to the first

40

the input of the delay block 17, the fourth control output of the block I is connected to the second input of the delay block 17, to the control inputs of the counter 15 and the delay block 18, the fifth control output of the block 1 is connected to the clock input of the counter 15, the first the input of block 1 is connected to the output of generator 16, to the third input of block 17 of delay and to the clock inputs of block 18 of delay and register 14, the second input of block 1 is connected to the output of block 17 of delay, the third input of block 1 is connected to the overflow output of counter 15 information inputs

RAM 13. After that, in the remote control 2, the Stop button is pressed and then all the processes are repeated until the information is stored in all the cells of RAM 13,

The operating mode of the generator is realized at the potential of a logical unit on the bus. Bus Mode. In this case

the counter 20 of the delay unit 18 is reset, and the triggers 9 and 10 and the element 2I-OR 8 express a pulse synchronous with the 5050 pulse. According to this impulse

the interval time code from the RAM 13 is written to the counter 15, and the other outputs of the RAM 13 (output crd) are written into the first register 19 of the delay unit 18. Some of them are connected to the first group 55; the programmable generator has N outputs of RAM 13, the second rpyhna of output channels (i.e., the output code of which is connected to the information RAM 13 contains N binary bits, delay inputs 18 in the drawing) then to the senior (K + 1) -th installation input of the register 14 soyodi bit of the first register 19 simultaneously

not the first control output of block 1, the control input of register 14 is connected to the first output of delay block 18, the remaining outputs of which are connected to information inputs of register 14, and in block 18 of delay 18 registers are connected in series, the bits of each of which are connected to information inputs of the respective switches 21, the address inputs of which are connected to the outputs of the counter 20, the control input of which is connected to the clock inputs of the registers 19, the clock input of the counter 20 is connected to the output of the first switch ora 21,

The programmable generator operates as follows.

When fed from console 2 to the bus. Potential zero logic mode, the programming mode is implemented. In this case, the register 14 ,. and with the help of the element IS-NE 6 the delay block 17 and the trigger 11 of block 1 are reset to the initial state. At the outputs of the counter 3 and at the inputs of the data Hbix RAM 13 are set the potentials specified from the console 2 defining the address of the RAM cell 13 and the code that you need to write in the cell, „„, „

When giving a logical unit from the remote control 2, the triggers 9 and 10 and the element 2И-OR 8 produce an impulse arriving through the element BAN 7 on

p ,, must be written in the cell, "", "

formations in the appropriate cell i

RAM 13. After that, in the remote control 2, the Stop button is pressed and then all the processes are repeated until the information is stored in all the cells of RAM 13,

The operating mode of the generator is realized at the potential of a logical unit on the bus Mode. In this case

the counter 20 of the delay unit 18 is reset, and the triggers 9 and 10 and the element 2I-OR 8 express a pulse synchronous with the clock pulse. According to this impulse

the interval duration code is written from the RAM 13 into the counter 15, and the other outputs of the RAM 13 (output crd) —the logical unit 12 — the logical unit of the output code is recorded in the manual. At the next clock pulses, the information in the first register 19 is sequentially shifted from the low bit to the high bit and then enters the next registers 19, also operating in the sequential shift mode. The pulse from the output of element 2I-OR 8 simultaneously increases by one the state of the counter 3 of block 1, and also enters the delay block 17, in which it is delayed by the time N-T, where T is the clock pulse repetition period. From the output of block 17, the delayed pulse arrives at the trigger 11 of block 1, which, through element 5, starts to pass clock pulses to counter 15. Having counted the number of pulses specified by the interval dipsity code, counter 15 outputs to the block 1 control the counting signal. According to this signal, trigger 11 and counter 3 stop the supply of clock pulses, and element 2I-LII 8 synchronizes with the next clock pulse, initializes the initial pulse, and all processes are repeated.

If the period T of the following clock pulses is selected from the conditions:

) -; Ss. i

where F- is the maximum frequency ccwCx KS

that counter is 15,

This ensures that the codes from RAM 13 are selected correctly and that counter 15 is working correctly. The output code of the (K + 1) -th interval will go to

first register 19 block 18 delay

to through time t Z1 (N-T + t;) after

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arrival there of the first interval code (C; - duration of the 1st interval). In block 18, the delay is the eVc delay of the output code (K + 1) -th interval at time t (M-K-1) -TN, where M is the greatest number of intervals worked by the programmable generator (in the drawing) .

Block 18 delay works as follows.

In the initial state, the upper N + 1 bits of the registers 19 are connected to the outputs of the switches 21. When, with a successive shift of the output codes in registers 19, except the first

At the first output of the switch 21, the output code of the first interval appears, then, at the next clock pulse, this code is written to the register 14, while the counter 20 increases its state by one and the switches 21 connect the next group of N + 1 bits to their outputs registers 19, except for the first register 19, but shifted by N + 1 bits. The code of the last interval goes to the outputs of switches 21 directly from the first register 19. If registers 19 have a total of (Ml) -N bits, then (K + 1) output code is delayed in them by rem t, the whole code in the register 14 (Bk -) - th slot is on the ET. c at times T., t, + t + tg (M-N) N T + Z; , where t d is some hardware delay, i.e. the moments of code occurrence are separated from each other by the exact duration of the corresponding interval — a short time interval is formed that is half as large as a sample of RAM information.

Claims (3)

1. A programmable pulse generator containing a control unit, a clock pulse generator, an operational storage device, an interval duration counter and a register whose setup input is connected to the first control output of the control unit, the data outputs and address outputs of which are connected to the information inputs and the address inputs of the random access memory, the first group of inputs which is connected to the information inputs of the counter for a long time, these intervals, characterized in that extension, the range of dpality generated by the pulses, it introduced the first and the second delay block, in which the first and second control outputs the control unit are connected to the first and second control inputs of the random access memory, the third control output of the control unit is connected to the first input of the first delay unit, the fourth control output of the control unit is connected with the second input of the first block delay and with the control inputs of the interval duration and second 51287254 the first delay control unit, the fifth control output of the control unit is connected to the clock input of the interval duration counter, the first input of the control unit is connected to the output of the clock pulse generator, to the third input of the first delay block and to the clock inputs of the second delay block and register, the second the input of the control unit is connected to the output of the first delay unit, the third input of the control unit is connected to the overflow output of the interval duration counter, and the second group of outputs of the random access memory by Keys to the data inputs of the second unit delay, adjusting input of the second delay unit coupled to an output Start the control unit, the register control input connected to the first output of the second delay unit, the other outputs are connected to data inputs of the register. 2. The generator according to claim 1, characterized in that the second delay unit contains serially connected registers, a pulse counter and switches, with the outputs 6 3. The generator according to claim 1, characterized in that the control unit comprises a console, a repeater unit, a pulse counter, the first and second AND elements, the NAND element, the BAN element, the 2I-OR element, the first, second and third triggers, the outputs of the console through the repeater unit are connected to the address inputs and to the control input of the pulse counter, to the first input of the NAND element, to the inputs of the first trigger and to the inverse input of the BANNER element, the output of the first trigger is connected to the second input of the H-NE and C element - to the entrance of the second trigger, which R-entrance is connected With the C-input of the pulse counter, with the direct input of the BANNER element, with the output of the element 2I-OR, and is the fourth output of the block, the output of the AND-NO element is the third output of the block and connected to the R input of the third trigger, C input of the third the trigger is connected to the first input of element 25 2I-OR, to the first input of the first element I and is the third input of the block, the S input of the third trigger is the second input of the block, the output of the third trigger is connected to the first 5 20 each of the registers is connected to the 30th input of the second element I, the second 0 7254 6 3. The generator according to claim 1, characterized in that the control unit comprises a console, a repeater unit, a pulse counter, the first and second AND elements, the NAND element, the BAN element, the 2I-OR element, the first, second and third triggers, and the outputs of the console through the repeater unit are connected to the address inputs and to the control input of the pulse counter, to the first input of the NAND element, to the inputs of the first trigger and to the inverse input of the BANNER element, the output of the first trigger is connected to the second input of the N-NE element and C- the second trigger input, the R input of which is connected With the C-input of the pulse counter, with the direct input of the BANNER element, with the output of the element 2I-OR, and is the fourth output of the block, the output of the AND-NO element is the third output of the block and connected to the R input of the third trigger, C input of the third the trigger is connected to the first input element 5 2I-OR, to the first input of the first element I and is the third input of the block, the S input of the third trigger is the second input of the block, the output of the third trigger is connected to the first 5 0 formation inputs of the corresponding switch, the address inputs of which are connected to the outputs of the pulse counter, the control input of which is connected to the clock inputs of the registers and is the clock input of the block. The control inputs of the registers are the control input of the block, the pulse input of the pulse counter is connected to the output of the first switch and the first output of the block, the remaining outputs of the switches are the output of the block, the setup input of the pulse counter is the installation input of the block. the input of which is the first input of the block and is connected to the second and third inputs of element 2И-OR, the fourth input of which is connected to the output of the second trigger, the output of the second element AND is five output, the inverse input and the output of the BAN element are respectively the first and second control the outputs of the block, the second input of the first element And is connected to the overflow output of the pulse counter, the outputs of which are information outputs, and the output of the first element And is connected to the input of the console.